PIC18F242 datasheet(213/332 Pages) MICROCHIP

213 / 332 page

DS39564C-page 211

PIC18FXX2

20.0

INSTRUCTION SET SUMMARY

The PIC18FXXX instruction set adds many enhance-

ments to the previous PICmicro instruction sets, while

maintaining an easy migration from these PICmicro

instruction sets.

Most instructions are a single program memory word

(16-bits), but there are three instructions that require

two program memory locations.

Each single word instruction is a 16-bit word divided

into an OPCODE, which specifies the instruction type

and one or more operands, which further specify the

operation of the instruction.

The instruction set is highly orthogonal and is grouped

into four basic categories:

• Byte-oriented operations

• Bit-oriented operations

• Literal operations

• Control operations

The PIC18FXXX instruction set summary in Table 20-2

lists byte-oriented, bit-oriented, literal and control

operations.

Table 20-1

shows

the

opcode

field

descriptions.

Most byte-oriented instructions have three operands:

The file register (specified by ‘f’)

The destination of the result

(specified by ‘d’)

The accessed memory

(specified by ‘a’)

The file register designator 'f' specifies which file

The destination designator ‘d’ specifies where the

result of the operation is to be placed. If 'd' is zero, the

result is placed in the WREG register. If 'd' is one, the

result is placed in the file register specified in the

instruction.

All bit-oriented instructions have three operands:

The file register (specified by ‘f’)

The bit in the file register

(specified by ‘b’)

The accessed memory

(specified by ‘a’)

The bit field designator 'b' selects the number of the bit

affected by the operation, while the file register desig-

nator 'f' represents the number of the file in which the

bit is located.

The literal instructions may use some of the following

operands:

• A literal value to be loaded into a file register

(specified by ‘k’)

• The desired FSR register to load the literal value

into (specified by ‘f’)

• No operand required

(specified by ‘—’)

The control instructions may use some of the following

operands:

• A program memory address (specified by ‘n’)

• The mode of the Call or Return instructions

(specified by ‘s’)

• The mode of the Table Read and Table Write

instructions (specified by ‘m’)

• No operand required

(specified by ‘—’)

All instructions are a single word, except for three dou-

ble-word instructions. These three instructions were

made double-word instructions so that all the required

information is available in these 32 bits. In the second

word, the 4-MSbs are 1’s. If this second word is exe-

cuted as an instruction (by itself), it will execute as a

NOP

All single word instructions are executed in a single

instruction cycle, unless a conditional test is true or the

program counter is changed as a result of the instruc-

tion. In these cases, the execution takes two instruction

cycles with the additional instruction cycle(s) executed

as a NOP.

The double-word instructions execute in two instruction

cycles.

One instruction cycle consists of four oscillator periods.

Thus, for an oscillator frequency of 4 MHz, the normal

instruction execution time is 1

μs. If a conditional test is

true or the program counter is changed as a result of an

instruction, the instruction execution time is 2

μs.

Two-word branch instructions (if true) would take 3

μs.

Figure 20-1 shows the general formats that the

instructions can have.

All examples use the format ‘nnh’

to represent a

hexadecimal

number,

where

‘h’

signifies

hexadecimal digit.

The Instruction Set Summary, shown in Table 20-2,

lists the instructions recognized by the Microchip

Assembler (MPASMTM).

Section 20.1 provides a description of each instruction.

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