PIC18F242 datasheet(209/332 Pages) MICROCHIP

209 / 332 page

DS39564C-page 207

PIC18FXX2

19.4

Program Verification and

Code Protection

The overall structure of the code protection on the

PIC18 FLASH devices differs significantly from other

PICmicro devices.

The user program memory is divided into five blocks.

One of these is a boot block of 512 bytes. The remain-

der of the memory is divided into four blocks on binary

boundaries.

Each of the five blocks has three code protection bits

associated with them. They are:

• Code Protect bit (CPn)

• Write Protect bit (WRTn)

• External Block Table Read bit (EBTRn)

Figure 19-3 shows the program memory organization

for 16- and 32-Kbyte devices, and the specific code

protection bit associated with each block. The actual

locations of the bits are summarized in Table 19-3.

FIGURE 19-3:

CODE PROTECTED PROGRAM MEMORY FOR PIC18F2XX/4XX

TABLE 19-3:

SUMMARY OF CODE PROTECTION REGISTERS

MEMORY SIZE/DEVICE

Block Code Protection

Controlled By:

16 Kbytes

(PIC18FX42)

32 Kbytes

(PIC18FX52)

Address

Range

Boot Block

000000h

0001FFh

CPB, WRTB, EBTRB

Block 0

000200h

001FFFh

CP0, WRT0, EBTR0

Block 1

002000h

003FFFh

CP1, WRT1, EBTR1

Unimplemented

Read 0’s

Block 2

004000h

005FFFh

CP2, WRT2, EBTR2

Unimplemented

Read 0’s

Block 3

006000h

007FFFh

CP3, WRT3, EBTR3

Unimplemented

Read 0’s

Unimplemented

Read 0’s

008000h

1FFFFFh

(Unimplemented Memory Space)

File Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

300008h

CONFIG5L

—

CP3

CP2

CP1

CP0

300009h

CONFIG5H

CPD

CPB

—

30000Ah

CONFIG6L

—

WRT3

WRT2

WRT1

WRT0

30000Bh

CONFIG6H

WRTD

WRTB

WRTC

—

30000Ch

CONFIG7L

—

EBTR3

EBTR2

EBTR1

EBTR0

30000Dh

CONFIG7H

—

EBTRB

—

Legend: Shaded cells are unimplemented.

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