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PIC18F242 Datasheet(PDF) 274 Page - Microchip Technology |
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PIC18F242 Datasheet(HTML) 274 Page - Microchip Technology |
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274 / 332 page ![]() PIC18FXX2 DS39564C-page 272 © 2006 Microchip Technology Inc. TABLE 22-5: PLL CLOCK TIMING SPECIFICATIONS (VDD = 4.2 TO 5.5V) FIGURE 22-6: CLKO AND I/O TIMING Param No. Sym Characteristic Min Typ† Max Units Conditions —FOSC Oscillator Frequency Range 4 — 10 MHz HS mode only —FSYS On-chip VCO System Frequency 16 — 40 MHz HS mode only —trc PLL Start-up Time (Lock Time) — — 2 ms — ΔCLK CLKO Stability (Jitter) -2 — +2 % † Data in “Typ” column is at 5V, 25 °C unless otherwise stated. These parameters are for design guidance only and are not tested. Note: Refer to Figure 22-4 for load conditions. OSC1 CLKO I/O Pin (input) I/O Pin (output) Q4 Q1 Q2 Q3 10 13 14 17 20, 21 19 18 15 11 12 16 Old Value New Value |
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