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S9S08AW60 Datasheet(PDF) 13 Page - Freescale Semiconductor, Inc |
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S9S08AW60 Datasheet(HTML) 13 Page - Freescale Semiconductor, Inc |
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13 / 324 page ![]() MC9S08AW60 Data Sheet, Rev 2 Freescale Semiconductor 13 Section Number Title Page 8.4.4 FLL Engaged Internal Unlocked ..................................................................................143 8.4.5 FLL Engaged Internal Locked ......................................................................................143 8.4.6 FLL Bypassed, External Clock (FBE) Mode ...............................................................143 8.4.7 FLL Engaged, External Clock (FEE) Mode .................................................................143 8.4.8 FLL Lock and Loss-of-Lock Detection ........................................................................144 8.4.9 FLL Loss-of-Clock Detection ......................................................................................145 8.4.10 Clock Mode Requirements ...........................................................................................146 8.4.11 Fixed Frequency Clock .................................................................................................147 8.4.12 High Gain Oscillator .....................................................................................................147 8.5 Initialization/Application Information ..........................................................................................147 8.5.1 Introduction ..................................................................................................................147 8.5.2 Example #1: External Crystal = 32 kHz, Bus Frequency = 4.19 MHz ........................149 8.5.3 Example #2: External Crystal = 4 MHz, Bus Frequency = 20 MHz ............................151 8.5.4 Example #3: No External Crystal Connection, 5.4 MHz Bus Frequency ....................153 8.5.5 Example #4: Internal Clock Generator Trim ................................................................155 Chapter 9 Keyboard Interrupt (S08KBIV1) 9.1 Introduction ...................................................................................................................................157 9.2 Keyboard Pin Sharing ....................................................................................................................157 9.3 Features .........................................................................................................................................158 9.3.1 KBI Block Diagram ......................................................................................................160 9.4 Register Definition ........................................................................................................................160 9.4.1 KBI Status and Control Register (KBI1SC) .................................................................161 9.4.2 KBI Pin Enable Register (KBI1PE) .............................................................................162 9.5 Functional Description ..................................................................................................................162 9.5.1 Pin Enables ...................................................................................................................162 9.5.2 Edge and Level Sensitivity ...........................................................................................162 9.5.3 KBI Interrupt Controls .................................................................................................163 Chapter 10 Timer/PWM (S08TPMV2) 10.1 Introduction ...................................................................................................................................165 10.2 Features .........................................................................................................................................165 10.2.1 Features .........................................................................................................................167 10.2.2 Block Diagram ..............................................................................................................167 10.3 External Signal Description ..........................................................................................................169 10.3.1 External TPM Clock Sources .......................................................................................169 10.3.2 TPMxCHn — TPMx Channel n I/O Pins .....................................................................169 10.4 Register Definition ........................................................................................................................169 10.4.1 Timer x Status and Control Register (TPMxSC) ..........................................................170 10.4.2 Timer x Counter Registers (TPMxCNTH:TPMxCNTL) .............................................171 |
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