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AS1117

Datasheet - D e t a i l e d D e s c r i p t i o n

Initial Power-Up

On initial power-up, the AS1117 registers are reset to their default values, the display is blanked, and the device goes

into shutdown mode. At this time, all registers should be programmed for normal operation.

Note:

The default settings enable only scanning of one digit; the internal decoder is disabled and the Intensity Control

Register (see page 17) is set to the minimum values.

Shutdown Mode

The AS1117 devices feature a shutdown mode, where they consume only 200nA (typ) current. Shutdown mode is

entered via a write to the Shutdown Register (see Table 8) or via pulling the pin RESTEN to logic low. When pin

RESETN is set to logic low an according write to the Shutdown Register is done internally. During shutdown mode the

Digit-Registers maintain their data.

Note:

When pin RESETN is pulled to logic high again, a write to the Shutdown Register in necessary to leave the

shutdown mode.

Shutdown mode can either be used as a means to reduce power consumption or for generating a flashing display

(repeatedly entering and leaving shutdown mode). For minimum supply current in shutdown mode, logic input should

When entering or leaving shutdown mode, the Feature Register is reset to its default values (all 0s) when Shutdown

Register bit D7 (page 13) = 0.

Note:

down mode. If the AS1117 is used with an external clock, Shutdown Register bit D7 should be set to 1 when

writing to the Shutdown Register.

Digit- and Control-Registers

The AS1117 devices contain 8 Digit-Registers,11 control-registers and 10 diagnostic-registers, which are listed in Table

7. All registers are selected using a 8-bit address word, and communication is done via the I²C interface.

!

Digit Registers – These registers are realized with an on-chip 64-bit memory. Each digit can be controlled directly

without rewriting the whole register contents.

!

Control Registers – These registers consist of decode mode, display intensity, number of scanned digits, shut-

down, display test and features selection registers.

Table 7. Register Address Map

Register

Address

Page

D15:D13

D12

D11

D10

D9

D8

D7:D0

Digit 0

000

0

0

0

0

1

(see Table 10 on page 14,

Table 11 on page 14 and

Table 12 on page 15)

N/A

Digit 1

000

0

0

0

1

0

N/A

Digit 2

000

0

0

0

1

1

N/A

Digit 3

000

0

0

1

0

0

N/A

Digit 4

000

0

0

1

0

1

N/A

Digit 5

000

0

0

1

1

0

N/A

Digit 6

000

0

0

1

1

1

N/A

Digit 7

000

0

1

0

0

0

N/A