www.austriamicrosystems.com/LED-Driver-ICs/AS1119

Revision 1.04

10 - 30

AS1119

Datasheet - Detailed Descr i pti on

I²C Interface

The AS1119 supports the I²C serial bus and data transmission protocol in fast mode at 1MHz. The AS1119 operates as a slave on the I²C bus.

The bus must be controlled by a master device that generates the serial clock (SCL), controls the bus access, and generates the START and

STOP conditions. Connections to the bus are made via the open-drain I/O pins SCL and SDA.

Figure 14. I²C Interface Initialisation

Figure 15. Bus Protocol

The bus protocol (as shown in Figure 15) is defined as:

- Data transfer may be initiated only when the bus is not busy.

- During data transfer, the data line must remain stable whenever the clock line is HIGH. Changes in the data line

while the clock line is HIGH will be interpreted as control signals.

The bus conditions are defined as:

- Bus Not Busy. Data and clock lines remain HIGH.

- Start Data Transfer. A change in the state of the data line, from HIGH to LOW, while the clock is HIGH, defines a

START condition.

- Stop Data Transfer. A change in the state of the data line, from LOW to HIGH, while the clock line is HIGH,

defines the STOP condition.

- Data Valid. The state of the data line represents valid data, when, after a START condition, the data line is stable

for the duration of the HIGH period of the clock signal. There is one clock pulse per bit of data.

Each data transfer is initiated with a START condition and terminated with a STOP condition. The number of data

bytes transferred between START and STOP conditions is not limited and is determined by the master device.

The information is transferred byte-wise and each receiver acknowledges with a ninth-bit.

Within the I²C bus specifications a high-speed mode (3.4MHz clock rate) is defined.

- Acknowledge: Each receiving device, when addressed, is obliged to generate an acknowledge after the recep-

tion of each byte. The master device must generate an extra clock pulse that is associated with this acknowledge

bit. A device that acknowledges must pull down the SDA line during the acknowledge clock pulse in such a way

that the SDA line is stable LOW during the HIGH period of the acknowledge clock pulse. Of course, setup and

hold times must be taken into account. A master must signal an end of data to the slave by not generating an

19

81

9

8

1

0

0

11

A1

A0 R/W

D15 D14 D13 D12 D11 D10

D9

D8

A0 and A1 are defined by the pins AD0 and AD1. Pin AD0 and AD1 must not be left floating.

SCL

SDA

SDI

SCL

Slave Address

R/W

Direction Bit

START

1

2

6

7

8

9

1

23-8

8

9

ACK

MSB

Repeat if More Bytes Transferred

STOP or

Repeated

START

ACK from

Receiver

ACK from

Receiver

ACK