PIC16F84A datasheet(307/337 Pages) MICROCHIP

307 / 337 page

DS30234D-page 307

PIC16C6X

APPENDIX A: MODIFICATIONS

The following are the list of modiﬁcations over the

PIC16C5X microcontroller family:

Instruction word length is increased to 14-bits.

This allows larger page sizes both in program

memory (2K now as opposed to 512 before) and

before).

A PC high latch register (PCLATH) is added to

handle program memory paging. PA2, PA1, PA0

bits are removed from STATUS register.

Data memory paging is redeﬁned slightly. STA-

TUS register is modiﬁed.

Four

new

instructions

have

been

added:

RETURN, RETFIE, ADDLW

, and SUBLW.

Two instructions TRIS and OPTION are being

phased out although they are kept for compati-

bility with PIC16C5X.

OPTION and TRIS registers are made address-

able.

Interrupt capability is added. Interrupt vector is

at 0004h.

Stack size is increased to 8 deep.

Reset vector is changed to 0000h.

Reset of all registers is revisited. Five different

reset (and wake-up) types are recognized. Reg-

isters are reset differently.

10. Wake-up from SLEEP through interrupt is

added.

11. Two separate timers, Oscillator Start-up Timer

(OST)

and

Power-up Timer

(PWRT),

are

included for more reliable power-up. These tim-

ers are invoked selectively to avoid unnecessary

delays on power-up and wake-up.

12. PORTB has weak pull-ups and interrupt on

change feature.

13. Timer0 pin is also a port pin (RA4/T0CKI) now.

14. FSR is made a full 8-bit register.

15. “In-circuit programming” is made possible. The

user can program PIC16CXX devices using only

ﬁve pins: VDD, VSS, VPP, RB6 (clock) and RB7

(data in/out).

16. Power Control register (PCON) is added with a

Power-on Reset status bit (POR).(Not on the

PIC16C61).

17. Brown-out Reset has been added to the follow-

ing devices:

PIC16C62A/R62/63/R63/64A/R64/65A/R65/66/

67.

APPENDIX B: COMPATIBILITY

To convert code written for PIC16C5X to PIC16CXX,

the user should take the following steps:

Remove any program memory page select

operations (PA2, PA1, PA0 bits) for CALL,

GOTO

Revisit any computed jump operations (write to

PC or add to PC, etc.) to make sure page bits

are set properly under the new scheme.

Eliminate any data memory page switching.

Redeﬁne data variables to reallocate them.

Verify all writes to STATUS, OPTION, and FSR

registers since these have changed.

Change reset vector to 0000h.

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