PIC16F84A datasheet(48/337 Pages) MICROCHIP

48 / 337 page

PIC16C6X

DS30234D-page 48

4.3

PCL and PCLATH

The program counter (PC) is 13-bits wide. The low byte

comes from the PCL register, which is a readable and

writable register. The upper bits (PC<12:8>) are not

readable, but are indirectly writable through the

PCLATH register. On any reset, the upper bits of the PC

will be cleared. Figure 4-24 shows the two situations for

the loading of the PC. The upper example in the ﬁgure

shows how the PC is loaded on a write to PCL

(PCLATH<4:0>

→ PCH). The lower example in the ﬁg-

ure shows how the PC is loaded during a CALL or GOTO

instruction (PCLATH<4:3>

→ PCH).

FIGURE 4-24: LOADING OF PC IN

DIFFERENT SITUATIONS

4.3.1

COMPUTED GOTO

A computed GOTO is accomplished by adding an offset

to the program counter (ADDWF PCL). When doing a

table read using a computed GOTO method, care

should be exercised if the table location crosses a PCL

memory boundary (each 256 word block). Refer to the

application note

“Implementing a Table Read” (AN556).

4.3.2

STACK

The PIC16CXX family has an 8 deep x 13-bit wide

hardware stack. The stack space is not part of either

program or data space and the stack pointer is not

readable or writable. The PC is PUSHed onto the stack

when a CALL instruction is executed or an interrupt

causes a branch. The stack is POPed in the event of a

RETURN,

RETLW

or a RETFIE instruction execution.

PCLATH is not affected by a PUSH or a POP operation.

The stack operates as a circular buffer. This means that

after the stack has been PUSHed eight times, the ninth

push overwrites the value that was stored from the ﬁrst

push. The tenth push overwrites the second push (and

so on).

Applicable Devices

61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67

PCLATH<4:0>

PCLATH

Instruction with

PCL as

ALU

GOTO, CALL

Opcode <10:0>

11 10

PCLATH<4:3>

PCH

PCL

PCLATH

PCH

PCL

destination

4.4

Program Memory Paging

PIC16C6X devices are capable of addressing a contin-

uous 8K word block of program memory. The CALL and

GOTO

instructions provide only 11 bits of address to

allow branching within any 2K program memory page.

When doing a CALL or GOTO instruction the upper two

bits of the address are provided by PCLATH<4:3>.

When doing a CALL or GOTO instruction, the user must

ensure that the page select bits are programmed so

that the desired program memory page is addressed. If

a return from a CALL instruction (or interrupt) is exe-

cuted, the entire 13-bit PC is pushed onto the stack.

Therefore, manipulation of the PCLATH<4:3> bits are

not required for the return instructions (which POPs the

address from the stack).

Note 1: There are no status bits to indicate stack

overﬂows or stack underﬂow conditions.

Note 2: There are no instructions mnemonics

called PUSH or POP. These are actions

that occur from the execution of the CALL,

RETURN,

RETLW,

and RETFIE instruc-

tions, or the vectoring to an interrupt

address

Applicable Devices

61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67

Note:

PIC16C6X devices with 4K or less of pro-

gram

memory

ignore

paging

bit

PCLATH<4>. The use of PCLATH<4> as a

general purpose read/write bit is not rec-

ommended since this may affect upward

compatibility with future products.

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