Electronic Components Datasheet Search
  New Zealand  ▼
ALLDATASHEET.CO.NZ

X  

AS3607 Datasheet(PDF) 58 Page - ams AG

Part # AS3607
Description  System PMU with HV Back Light Driver
PDF  71 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  AMSCO [ams AG]
Direct Link  http://www.ams.com
Logo AMSCO - ams AG

AS3607 Datasheet(HTML) 58 Page - ams AG

Back Button AS3607 Datasheet HTML 54Page - ams AG AS3607 Datasheet HTML 55Page - ams AG AS3607 Datasheet HTML 56Page - ams AG AS3607 Datasheet HTML 57Page - ams AG AS3607 Datasheet HTML 58Page - ams AG AS3607 Datasheet HTML 59Page - ams AG AS3607 Datasheet HTML 60Page - ams AG AS3607 Datasheet HTML 61Page - ams AG AS3607 Datasheet HTML 62Page - ams AG Next Button
Zoom Inzoom in Zoom Outzoom out
 58 / 71 page
background image
www.austriamicrosystems.com
Revision 1.03
57 - 70
AS3606 AS3607 2v2
Data Sheet - R e g i s t e r D e f i n i t i o n
Table 49. Second Interrupt Register
Name
Base
Default
IRQENRD_1
2-wire serial
00h
Offset: 24h
Second Interrupt Register
Please be aware that writing to this register will enable/disable the corresponding
interrupts, while reading gets the actual interrupt status and will clear the register at the
same time. It is not possible to read back the interrupt enable/disable settings. This register is
reset at a VDD27-POR or XRES input.
Bit
Bit Name
Default
Access
Bit Description
7
PWRUP_IRQ
0
W
Enables interrupt which is invoked whenever a high signal at the PWRUP
input pin occurs
0: disable
1: enable
x
R
This bit is set whenever a high level of min. VSUP/3 at the PWRUP input pin
occurs (PWRUP pin is commonly connected to the power-up button)
6
GPIO1_IRQ
0
W
Enables interrupt which is invoked whenever a high signal at the GPIO1
input pin occurs
0: disable
1: enable
x
R
This bit is set whenever a high level of min. tbd at the GPIO1 input pin
occurs
5
GPIO2_IRQ
0
W
Enables interrupt which is invoked whenever a high signal at the GPIO2
input pin occurs
0: disable
1: enable
x
R
This bit is set whenever a high level of min. tbd at the GPIO2 input pin
occurs
4
GPIO3_IRQ
0
W
Enables interrupt which is invoked whenever a high signal at the GPIO3
input pin occurs
0: disable
1: enable
x
R
This bit is set whenever a high level of min. tbd at the GPIO3 input pin
occurs
3
GPIO4_IRQ
0
W
Enables interrupt which is invoked whenever a high signal at the GPIO4
input pin occurs
0: disable
1: enable
x
R
This bit is set whenever a high level of min. tbd at the GPIO4 input pin
occurs
2:0
-
000
n/a



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71


Datasheet Download

Go To PDF Page


Link URL



Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Contact us   |   Privacy Policy   |   Link to Datasheet    |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com