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AS3668

Data Sheet - Electrical Characteristics

6.1 Timing Characteristics

VBAT = 3.6V, CBAT = CVCPOUT = 1μF, CFLY = 470nF, TAMB = -30ºC to +85ºC, typical values @ TAMB = +25ºC (unless

otherwise specified) .

Table 4. Electrical Characteristics I

2C1

1. Specification is guaranteed by design and is not tested in production. VEN = 1.65V to VBAT.

Symbol

Parameter

Condition

Min

Typ

Max

Unit

I2C mode timings - see

fSCLK

SCL Clock Frequency

1/35ms

400

kHz

tBUF

Bus Free Time Between a

STOP and START

Condition

1.3

μs

tHD:STA

Hold Time (Repeated)

START Condition

2. After this period the first clock pulse is generated.

0.6

μs

tLOW

LOW Period of SCL Clock

1.3

μs

tHIGH

HIGH Period of SCL Clock

0.6

μs

tSU:STA

Setup Time for a Repeated

START Condition

0.6

μs

tHD:DAT

Data Hold Time

3. A device must internally provide a hold time of at least 300ns for the SDA signal (referred to the VIHMIN of the SCLK signal) to bridge the

undefined region of the falling edge of SCLK.

0.9

μs

tSU:DAT

Data Setup Time

4. A fast-mode device can be used in a standard-mode system, but the requirement tSU:DAT = to 250ns must then be met. This is automat-

ically the case if the device does not stretch the LOW period of the SCLK signal. If such a device does stretch the LOW period of the

SCLK signal, it must output the next data bit to the SDA line tR max + tSU:DAT = 1000 + 250 = 1250ns before the SCLK line is released.

100

Rise Time of Both SDA and

SCL Signals

20 +

0.1CB

300

Fall Time of Both SDA and

SCL Signals

20 +

0.1CB

300

tSU:STO

Setup Time for STOP

Condition

0.6

μs

Capacitive Load for Each

Bus Line

CB — total capacitance of one bus line in pF

400

CI/O

I/O Capacitance (SDA,

SCL)

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