Electronic Components Datasheet Search
  New Zealand  ▼
ALLDATASHEET.CO.NZ

X  

TCS3472 Datasheet(PDF) 6 Page - ams AG

Part # TCS3472
Description  COLOR LIGHT-TO-DIGITAL CONVERTER with IR FILTER
PDF  27 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  AMSCO [ams AG]
Direct Link  http://www.ams.com
Logo AMSCO - ams AG

TCS3472 Datasheet(HTML) 6 Page - ams AG

Back Button TCS3472 Datasheet HTML 2Page - ams AG TCS3472 Datasheet HTML 3Page - ams AG TCS3472 Datasheet HTML 4Page - ams AG TCS3472 Datasheet HTML 5Page - ams AG TCS3472 Datasheet HTML 6Page - ams AG TCS3472 Datasheet HTML 7Page - ams AG TCS3472 Datasheet HTML 8Page - ams AG TCS3472 Datasheet HTML 9Page - ams AG TCS3472 Datasheet HTML 10Page - ams AG Next Button
Zoom Inzoom in Zoom Outzoom out
 6 / 27 page
background image
TCS3472
COLOR LIGHT-TO-DIGITAL CONVERTER
with IR FILTER
TAOS135 − AUGUST 2012
5
The LUMENOLOGY
r Company
r
r
Copyright
E 2012, TAOS Inc.
www.taosinc.com
Wait Characteristics, VDD = 3 V, TA = 255C, WEN = 1 (unless otherwise noted)
PARAMETER
TEST CONDITIONS
CHANNEL
MIN
TYP
MAX
UNIT
Wait step size
WTIME = 0xFF
2.27
2.4
2.56
ms
Wait number of integration steps (Note 1)
1
256
steps
NOTE 1: Parameter ensured by design and is not tested.
AC Electrical Characteristics, VDD = 3 V, TA = 255C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
f(SCL)
Clock frequency (I2C only)
0
400
kHz
t(BUF)
Bus free time between start and stop condition
1.3
μs
t(HDSTA)
Hold time after (repeated) start condition. After
this period, the first clock is generated.
0.6
μs
t(SUSTA)
Repeated start condition setup time
0.6
μs
t(SUSTO)
Stop condition setup time
0.6
μs
t(HDDAT)
Data hold time
0
μs
t(SUDAT)
Data setup time
100
ns
t(LOW)
SCL clock low period
1.3
μs
t(HIGH)
SCL clock high period
0.6
μs
tF
Clock/data fall time
300
ns
tR
Clock/data rise time
300
ns
Ci
Input pin capacitance
10
pF
Specified by design and characterization; not production tested.
PARAMETER MEASUREMENT INFORMATION
Start
Condition
Stop
Condition
P
SDA
t(SUSTO)
t(SUDAT)
t(HDDAT)
t(BUF)
VIH
VIL
SCL
t(SUSTA)
t(HIGH)
t(F)
t(R)
t(HDSTA)
t(LOW)
VIH
VIL
PS
S
Figure 1. Timing Diagrams



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27


Datasheet Download

Go To PDF Page


Link URL



Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Contact us   |   Privacy Policy   |   Link to Datasheet    |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com