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TSL2771 Datasheet(PDF) 6 Page - ams AG

Part # TSL2771
Description  LIGHT-TO-DIGITAL CONVERTER with PROXIMITY SENSING
PDF  33 Pages
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Manufacturer  AMSCO [ams AG]
Direct Link  http://www.ams.com
Logo AMSCO - ams AG

TSL2771 Datasheet(HTML) 6 Page - ams AG

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TSL2771
LIGHT-TO-DIGITAL CONVERTER
with PROXIMITY SENSING
TAOS100B − FEBRUARY 2011
5
The LUMENOLOGY
r Company
r
r
Copyright
E 2011, TAOS Inc.
www.taosinc.com
Proximity Characteristics, VDD = 3 V, TA = 255C, PEN = 1 (unless otherwise noted)
PARAMETER
TEST CONDITIONS
CONDITION
MIN
TYP
MAX
UNIT
IDD
Supply current
LDR pulse on
3
mA
ADC conversion time step size
PTIME = 0xFF
2.58
2.72
2.9
ms
ADC number of integration steps
1
256
steps
ADC counts per step
PTIME = 0xFF
0
1023
counts
IR LED pulse count
0
255
pulses
pulse period
Two or more pulses
16
μs
LED pulse width — LED on time
7.3
μs
PDRIVE=0
75
100
125
LED drive current
ISINK sink current @ 600 mV,
PDRIVE=1
50
mA
LED drive current
ISINK sink current @ 600 mV,
LDR pin
PDRIVE=2
25
mA
PDRIVE=3
12.5
Operating distance (See note 1)
18
inches
NOTE 1: Proximity Operating Distance is dependent upon emitter properties and the reflective properties of the proximity surface. The nominal
value shown uses an IR emitter with a peak wavelength of 850nm and a 20
° half angle. The proximity surface used is a 90% reflective
(white surface) 16
× 20-inch Kodak Gray Card. 60 mw/SR, 100 mA, 64 pulses, open view (no glass). Note: Greater distances are
achievable with appropriate system considerations.
Wait Characteristics, VDD = 3 V, TA = 255C, WEN = 1 (unless otherwise noted)
PARAMETER
TEST CONDITIONS
CHANNEL
MIN
TYP
MAX
UNIT
Wait step size
WTIME = 0xFF
2.58
2.72
2.9
ms
Wait number of integration steps
1
256
steps
AC Electrical Characteristics, VDD = 3 V, TA = 255C (unless otherwise noted)
PARAMETER†
TEST CONDITIONS
MIN
TYP
MAX
UNIT
f(SCL)
Clock frequency (I2C only)
0
400
kHz
t(BUF)
Bus free time between start and stop condition
1.3
μs
t(HDSTA)
Hold time after (repeated) start condition. After
this period, the first clock is generated.
0.6
μs
t(SUSTA)
Repeated start condition setup time
0.6
μs
t(SUSTO)
Stop condition setup time
0.6
μs
t(HDDAT)
Data hold time
0
μs
t(SUDAT)
Data setup time
100
ns
t(LOW)
SCL clock low period
1.3
μs
t(HIGH)
SCL clock high period
0.6
μs
tF
Clock/data fall time
300
ns
tR
Clock/data rise time
300
ns
Ci
Input pin capacitance
10
pF
† Specified by design and characterization; not production tested.



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