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AT45DB080 Datasheet(PDF) 7 Page - ATMEL Corporation |
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AT45DB080 Datasheet(HTML) 7 Page - ATMEL Corporation |
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7 / 18 page  AT45DB080 7 AC Waveforms Two different timing diagrams are shown below. Waveform 1 shows the CLK signal being low when CS makes a high- to-low transition, and Waveform 2 shows the CLK signal being high when CS makes a high-to-low transition. Both waveforms show valid timing diagrams. The setup and hold times for the SI signal are referenced to the low-to-high transition on the CLK signal. Waveform 1 – Inactive Clock Polarity Low Waveform 2 – Inactive Clock Polarity High CS CLK I/O7-I/O0 (INPUT) I/O7-I/O0 (OUTPUT) tCSS VALID IN tH tSU tWH tWL tCSH tCS tV HIGH IMPEDANCE VALID OUT tHO tDIS HIGH IMPEDANCE CS CLK I/O7-I/O0 (INPUT) I/O7-I/O0 (OUTPUT) tCSS VALID IN tH tSU tWL tWH tCSH tCS tV HIGH Z VALID OUT tHO tDIS HIGH IMPEDANCE |
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