AT45DB321

10

Reset Timing (Inactive Clock Polarity Low Shown)

Command Sequence for Read/Write Operations (Except Status Register Read)

Notes:

1.

“r” designates bits reserved for larger densities.

2.

It is recommended that “r” be a logical “0” for densities of 32M bit or smaller.

3.

For densities larger than 32M bit, the “r” bits become the most significant Page Address bit for the appropriate density.

CS

SCK

RESET

SO

SI

HIGH IMPEDANCE

HIGH IMPEDANCE

SI

CMD

8 bits

8 bits

8 bits

MSB

Reserved for

larger densities

Page Address

(PA12-PA0)

Byte/Buffer Address

(BA9-BA0/BFA9-BFA0)

LSB

r X X X X X X X

X X X X X X X X

X X X X X X X X