SPC5601PEF0MLH6R datasheet(55/95 Pages) FREESCALE

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MPC5602P Microcontroller Data Sheet, Rev. 4.1

Freescale Semiconductor

tCYC

D System clock period

—

1 / fSYS

fLORL

D Loss of reference frequency window3

Lower limit

1.6

3.7

MHz

fLORH

Upper limit

fSCM

D Self-clocked mode frequency4,5

—

150

MHz

CJITTER

T CLKOUT period

jitter6,7,8,9

Short-term jitter10

fSYS maximum

44

% fCLKOUT

Long-term jitter

(average over 2 ms

interval)

fPLLIN =16MHz

(resonator), fPLLCLK at

64 MHz, 4000 cycles

—10

tlpll

D PLL lock time11, 12

—

200

µs

tdc

D Duty cycle of reference

—

fLCK

D Frequency LOCK range

—

66

% fSYS

fUL

D Frequency un-LOCK range

—

18

% fSYS

fCS

D Modulation depth

Center spread

±0.25

±4.013

%fSYS

fDS

Down spread

0.5

8.0

fMOD

D Modulation frequency14

—

kHz

1 VDD_LV_CORx = 1.2 V ±10%; VSS = 0 V; TA = –40 to 125 °C, unless otherwise specified

2 Considering operation with PLL not bypassed.

3 “Loss of Reference Frequency” window is the reference frequency range outside of which the PLL is in self clocked

mode.

4 Self clocked mode frequency is the frequency that the PLL operates at when the reference frequency falls outside

the fLOR window.

5 fVCO self clock range is 20–150 MHz. fSCM represents fSYS after PLL output divider (ERFD) of 2 through 16 in

enhanced mode.

6 This value is determined by the crystal manufacturer and board design.

7 Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum

fSYS. Measurements are made with the device powered by filtered supplies and clocked by a stable external clock

signal. Noise injected into the PLL circuitry via VDD_LV_COR0 and VSS_LV_COR0 and variation in crystal oscillator

frequency increase the CJITTER percentage for a given interval.

8 Proper PC board layout procedures must be followed to achieve specifications.

9 Values are obtained with frequency modulation disabled. If frequency modulation is enabled, jitter is the sum of

CJITTER and either fCS or fDS (depending on whether center spread or down spread modulation is enabled).

10 Short term jitter is measured on the clock rising edge at cycle n and cycle n+4.

11 This value is determined by the crystal manufacturer and board design. For 4 MHz to 20 MHz crystals specified for

this PLL, load capacitors should not exceed these limits.

12 This specification applies to the period required for the PLL to relock after changing the MFD frequency control bits

in the synthesizer control register (SYNCR).

13 This value is true when operating at frequencies above 60 MHz, otherwise fCS is 2% (above 64 MHz).

14 Modulation depth will be attenuated from depth setting when operating at modulation frequencies above 50 kHz.

Table 26. FMPLL electrical characteristics (continued)

Symbol

Parameter

Conditions1

Value

Unit

Min

Max

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