AT73C500 datasheet(21/28 Pages) ATMEL

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AT73C500

AT73C500 provides four handshaking signals, ADDR1,

RD/WR, STROBE and BRDY, for interfacing with the

microprocessor. Microprocessor can use the BRDY input of

AT73C500 to extend the read and write cycles. AT73C500

stays in the read or write mode as long as BRDY is high.

BRDY is sampled at the rising edge of AT73C500 master

clock. As soon as BRDY goes low, the read/write cycle of

AT73C500 will end at the first rising edge of CLK clock.

During read operation data is latched into AT73C500 regis-

ter on the rising edge of the STROBE signal following the

low level of BRDY. A more detailed description about the

handshake signals is presented in section “Data Transfer

to External Microprocessor” on page 12.

Fifteen idle cycles are inserted by AT73C500 between the

read operation of each calibration byte. This allows the pro-

cessor to prepare the next coefficient for transfer or to raise

the BRDY signal in case it is not ready to write the following

byte. If the data is available, BRDY can be kept constantly

low. Microprocessor has to always supply all 44 calibration

bytes even though some of those may be zero and don't

affect to measurement results.

If AT73C500 detects an error when comparing the calibra-

tion data and corresponding back-up values, it writes the

DATRDY bit high and after that the header bytes on pro-

cessor bus indicating that it is still in initialization routine

and wishes to get the calibration data to be transported

once again. If the error still exists after the third trial,

AT73C500 notifies the situation by a FAIL status bit and

starts normal operation, discarding potentially incorrect cal-

ibration coefficients.

If AT73C500 is programmed to mode 1 or 2, the coeffi-

cients are stored in an EEPROM of type AT93C46. The

ROM has to support communication through a three pin

serial I/O port. The serial ROM interface uses the same

po r t,

which

also

conne cts

AT 73C 500

AT73C501/AT73C502 sample output. During the initializa-

tion phase, the ADC interface has to be disabled. This can

be done by B8 bit of AT73C500 Status bus (ADDR0). The

output has to be latched by an external flip-flop to keep the

state over the whole initialization period. The same output

can be used as Chip Select input for the EEPROM.

AT73C500 reads, checks and stores automatically all 44

calibration coefficients. After that, B8 bit of Status byte is

written low and normal measurement can start. If the

EEPROM contains erroneous data and one or more coeffi-

cients don’t match with their back-up values, the same pro-

cedure is followed as in the processor mode.

Gain Calibration

Gain calibration is used to compensate the accumulated

magnitude error of voltage dividers, current transformers

and A/D converters. There is a separate 8-bit gain calibra-

tion coefficient for each phase, and for active and reactive

energy measurement. A similar formula is also used to cal-

ibrate the phase voltage values, only the calibration range

is different, 20% for power and 8% for voltage. These cali-

brations will automatically correct the gain error of other

measurement parameters.

The following calculations are done to get the calibrated

results. For active power:

where PN is the active power of phase N and AGCN is the

gain calibration factor of that phase. The valid range for

AGC

N is -128 to +127. Similarly, for reactive power:

where QN is the reactive power of phase N and RGCN is

the gain calibration coefficient for that phase. RGC

N valid

range is -128 to +127.

Gain calibration performed on voltage measurements are:

where UN is the line voltage of phase N and UGCN is the

corresponding gain calibration coefficient, ranging from

-128 to +127.

Apparent power and current are automatically gain

adjusted to match the calibrated settings of active power,

reactive power and voltage.

Offset Calibration

The low current response of current sensors is often more

or less non-linear. The error caused by this non-linearity

can be compensated by a small offset factor which is

added in power results. Offset calibration is done for active

and reactive power, separately for each phase. The follow-

ing formulas are used:

and

where PN and QN are the active and reactive power for

phase N, AOF

N and ROFN are the respective offset calibra-

tion coefficients and P

FS and QFS are the corresponding full

10.2

AGC

128

----------------





10.2

RGC

128

-----------------





10.08

UGC

128

-----------------





AOF

128

----------------

0.004157

sign

N)PFS

≡

ROF

128

----------------

0.00457

sign(Q

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