AT90LS2323-4SC datasheet(32/64 Pages) ATMEL

32 / 64 page

AT90S/LS2323/2343

1004D–09/01

EEPROM Read/Write

Access

The EEPROM access registers are accessible in the I/O space.

The write access time is in the range of 2.5 - 4 ms, depending on the V

CC voltages. A

self-timing function, however, lets the user software detect when the next byte can be

written.

In order to prevent unintentional EEPROM writes, a specific write procedure must be fol-

lowed. Refer to the description of the EEPROM Control Register for details on this.

When the EEPROM is written, the CPU is halted for two clock cycles before the next

instruction is executed. When the EEPROM is read, the CPU is halted for four clock

cycles before the next instruction is executed.

EEPROM Address Register –

EEAR

• Bit 7 – Res: Reserved Bit

This bit is a reserved bit in the AT90S2323/2343 and will always read as zero.

• Bit 6..0 – EEAR6..0: EEPROM Address

The EEPROM Address Register (EEAR6..0) specifies the EEPROM address in the

128-byte EEPROM space. The EEPROM data bytes are addressed linearly between 0

and 127.

EEPROM Data Register –

EEDR

• Bits 7..0 – EEDR7..0: EEPROM Data

For the EEPROM write operation, the EEDR register contains the data to be written to

the EEPROM in the address given by the EEAR register. For the EEPROM read opera-

tion, the EEDR contains the data read out from the EEPROM at the address given by

EEAR.

Bit

765

432

$1E ($3E)

–

EEAR6

EEAR5

EEAR4

EEAR3

EEAR2

EEAR1

EEAR0

EEAR

Read/Write

R/W

Initial Value

Bit

765

432

$1D ($3D)

MSB

LSB

EEDR

Read/Write

R/W

Initial Value

AT90LS2323-4SC Datasheet(PDF) 32 Page - ATMEL Corporation

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