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CAT28F010 Datasheet(PDF) 13 Page - Catalyst Semiconductor |
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CAT28F010 Datasheet(HTML) 13 Page - Catalyst Semiconductor |
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13 / 14 page ![]() CAT28F010 13 Doc. No. 25005-0A 2/98 F-1 28F010 F10 ADDRESSES WE (E) OE (G) CE (W) DATA (I/O) VCC VPP tWC tWC tRC tAVEL tELAX tWLEL tWLEL tEHQZ tDF tGHEL tEHEL tEHEH tEHGL tELEH HIGH-Z DATA IN = 40H DATA IN DATA IN = C0H VALID DATA OUT tEHDX tOLZ tOE tOH tLZ tCE tVPEL VPPH VPPL 0V 5.0V VCC POWER-UP & STANDBY SETUP PROGRAM COMMAND LATCH ADDRESS & DATA PROGRAMMING PROGRAM VERIFY COMMAND PROGRAM VERIFICATION VCC POWER-DOWN/ STANDBY tWLEL tEHWH tEHWH tEHWH tELEH tDVEH tDVEH tDVEH tEHDX tEHDX (W) (E) Program-Verify Mode A Program-verify cycle is performed to ensure that all bits have been correctly programmed following each byte programming operation. The specific address is already latched from the write cycle just completed, and stays latched until the verify is completed. The Program- verify operation is initiated by writing C0H into the command register. An internal reference generates the necessary high voltages so that the user does not need to modify VCC. Refer to AC Characteristics (Program/ Erase) for specific timing parameters. Abort/Reset An Abort/Reset command is available to allow the user to safely abort an erase or program sequence. Two consecutive program cycles with FFH on the data bus will abort an erase or a program operation. The abort/ reset operation can interrupt at any time in a program or erase operation and the device is reset to the Read Mode. POWER UP/DOWN PROTECTION The CAT28F010 offers protection against inadvertent programming during VPP and VCC power transitions. When powering up the device there is no power-on sequencing necessary. In other words, VPP and VCC may power up in any order. Additionally VPP may be hardwired to VPPH independent of the state of VCC and any power up/down cycling. The internal command register of the CAT28F010 is reset to the Read Mode on power up. POWER SUPPLY DECOUPLING To reduce the effect of transient power supply voltage spikes, it is good practice to use a 0.1 µF ceramic capacitor between VCC and VSS and VPP and VSS. These high-frequency capacitors should be placed as close as possible to the device for optimum decoupling. Figure 8. Alternate A.C. Timing for Program Operation |
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