CAT93C57PI-TE13 datasheet(6/9 Pages) CATALYST

6 / 9 page

93C46/56/57/66/86

Doc. No. 25056-00 2/98 M-1

The format for all instructions sent to the device is a

logical "1" start bit, a 2-bit (or 4-bit) opcode, 6-bit (93C46)/

/7-bit (93C57)/ 8-bit (93C56 or 93C66)/10-bit (93C86)

(an additional bit when organized X8) and for write

operations a 16-bit data field (8-bit for X8 organizations).

Note: This note is applicable only to 93C86. The Write,

Erase, Write all and Erase all instructions require PE=1.

If PE is left floating, 93C86 is in Program Enabled mode.

For Write Enable and Write Disable instruction PE=don’t

care.

Read

Upon receiving a READ command and an address

(clocked into the DI pin), the DO pin of the CAT93C46/

56/57/66/86 will come out of the high impedance state

and, after sending an initial dummy zero bit, will begin

shifting out the data addressed (MSB first). The output

data bits will toggle on the rising edge of the SK clock and

are stable after the specified time delay (tPD0 or tPD1)

For the 93C56/57/66/86, after the initial data word has

been shifted out and CS remains asserted with the SK

clock continuing to toggle, the device will automatically

increment to the next address and shift out the next data

word in a sequential READ mode. As long as CS is

continuously asserted and SK continues to toggle, the

device will keep incrementing to the next address auto-

matically until it reaches to the end of the address space,

then loops back to address 0. In the sequential READ

mode, only the initial data word is preceeded by a

dummy zero bit. All subsequent data words will follow

without a dummy zero bit.

Write

After receiving a WRITE command, address and the

data, the CS (Chip Select) pin must be deselected for a

minimum of tCSMIN. The falling edge of CS will start the

self clocking clear and data store cycle of the memory

location specified in the instruction. The clocking of the

SK pin is not necessary after the device has entered the

self clocking mode. The ready/busy status of the

CAT93C46/56/57/66/86 can be determined by selecting

the device and polling the DO pin. Since this device

features Auto-Clear before write, it is NOT necessary to

erase a memory location before it is written into.

Figure 3. Write Instruction Timing

93C46/56/57/66/86 F05

Figure 2b. Read Instruction Timing (93C56/57/66/86)

tCS

STANDBY

HIGH-Z

101

AN AN-1

BUSY

READY

STATUS

VERIFY

tSV

tHZ

tEW

HIGH-Z

AN AN–1

Dummy 0

D15 . . . D0

D7 . . . D0

1111111

Address + 1

D15 . . . D0

D7 . . . D0

Address + 2

D15 . . . D0

D7 . . . D0

Address + n

D15 . . .

D7 . . .

Don't Care

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