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THS4052CD Datasheet(PDF) 17 Page - National Semiconductor (TI) |
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THS4052CD Datasheet(HTML) 17 Page - National Semiconductor (TI) |
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17 / 36 page ![]() THS4051 THS4052 SLOS238D − MAY 1999 − REVISED AUGUST 2008 www.ti.com 17 APPLICATION INFORMATION DRIVING A CAPACITIVE LOAD Driving capacitive loads with high performance amplifiers is not a problem as long as certain precautions are taken. The first is to realize that the THS405x has been internally compensated to maximize its bandwidth and slew rate performance. When the amplifier is compensated in this manner, capacitive loading directly on the output will decrease the device’s phase margin leading to high frequency ringing or oscillations. Therefore, for capacitive loads of greater than 10 pF, it is recommended that a resistor be placed in series with the output of the amplifier, as shown in Figure 45. A minimum value of 20 Ω should work well for most applications. For example, in 75-Ω transmission systems, setting the series resistor value to 75 Ω both isolates any capacitance loading and provides the proper line impedance matching at the source end. + _ THS405x CLOAD 1 k Ω Input Output 1 k Ω 20 Ω Figure 45. Driving a Capacitive Load OFFSET NULLING The THS405x has very low input offset voltage for a high-speed amplifier. However, if additional correction is required, an offset nulling function has been provided on the THS4051. The input offset can be adjusted by placing a potentiometer between terminals 1 and 8 of the device and tying the wiper to the negative supply. This is shown in Figure 46. _ + THS4051 VCC − VCC+ 0.1 µF 0.1 µF 10 k Ω Figure 46. Offset Nulling Schematic |
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