L4995 datasheet(19/35 Pages) STMICROELECTRONICS

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L4995

Application information

Doc ID 13103 Rev 14

19/35

Reset is active when En is high.

Figure 29.

Reset timing diagram

3.3

Watchdog

A connected microcontroller is monitored by the watchdog input Wi. If pulses are missing,

the Reset output pin is set to low. The pulse sequence time can be set within a wide range

with the external capacitor, Ctw. The watchdog circuit discharges the capacitor Ctw, with the

constant current Icwd. If the lower threshold Vwlth is reached, a watchdog reset is generated.

To prevent this the microcontroller must generate a positive edge during the discharge of the

capacitor before the voltage has reached the threshold Vwlth. In order to calculate the

minimum time t, during which the micro-controller must output the positive edge, the

following equation can be used:

Equation 3

(Vwhth-Vwlth) x Ctw = Icwd x t

Every Wi positive edge switches the current source from discharging to charging. The same

happens when the lower threshold is reached. When the voltage reaches the upper

threshold, Vwhth, the current switches from charging to discharging. The result is a saw-tooth

voltage at the watchdog timer capacitor Ctw.

Figure 30.

Watchdog timing diagram

trr

< trr

trd

Tosc

Vrhth

Vrlth

Res

Vcr

Vout_th

trr

< trr

trd

Tosc

Vrhth

Vrlth

Res

Vcr

Vout_th

GAPGMS00077

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