CS8127YDR8 datasheet(4/6 Pages) CHERRY

4 / 6 page

The CS8127

function is very precise, has hysteresis

on both the

and Delay comparators, a latching

Delay capacitor discharge circuit, and operation down to

1V.

The reset circuit output is an open collector type with ON

and OFF parameters as specified. The reset output NPN

transistor is controlled by the Low Voltage Inhibit and

Reset Delay circuits (see Block Diagram).

This circuit monitors output voltage, and when output

voltage is below VRTL, causes the reset output transistor to

be in the ON (saturation) state. When the output voltage is

above VRTH, this circuit permits the reset output transistor

to go into the OFF state if allowed by the reset Delay cir-

cuit.

This circuit provides a programmable (by external capaci-

tor) delay on the

output lead. The Delay lead pro-

vides source current to the external delay capacitor only

when the Low Voltage Inhibit circuit indicates that output

voltage is above VRTH. Otherwise, the Delay lead sinks

current to ground (used to discharge the Delay capacitor).

The discharge current is latched ON when the output volt-

age falls below VRTL. The Delay capacitor is fully dis-

charged anytime the output voltage falls out of regulation,

even for a short period of time. This feature ensures a con-

trolled

pulse is generated following the detection

of an error condition. The circuit allows the

out-

put transistor to go to the OFF (open) state only when the

voltage on the Delay lead is higher than VDTC.

RESET

RESET Delay Circuit

Low Voltage Inhibit Circuit

RESET

VRH

VOUT

VRTH

VRTL

VRL

Delay

VDTC

VDTD

VDH

VDIS

(3)

(1)

(2)

RESET Circuit Waveform

RESET Circuit Functional Description

(1) = No Delay Capacitor

(2) = With Delay Capacitor

(3) = Max: RESET Voltage (1.0V)

CS8127YDR8 Datasheet(PDF) 4 Page - Cherry Semiconductor Corporation

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