AT25DF021-MH-T datasheet(4/41 Pages) ETC2

4 / 41 page

3677F–DFLASH–5/2013

AT25DF021

3. Block Diagram

Figure 3-1.

Block Diagram

4. Memory Array

To provide the greatest flexibility, the memory array of the AT25DF021 can be erased in four lev-

els of granularity including a full chip erase. In addition, the array has been divided into physical

sectors of uniform size, of which each sector can be individually protected from program and

erase operations. The size of the physical sectors is optimized for both code and data storage

applications, allowing both code and data segments to reside in their own isolated regions. The

Memory Architecture Diagram illustrates the breakdown of each erase level as well as the

breakdown of each physical sector.

Figure 2-1.

8-SOIC Top View

Figure 2-2.

8-UDFN (Top View)

GND

VCC

HOLD

SCK

GND

VCC

HOLD

SCK

FLASH

MEMORY

ARRAY

Y-GATING

SCK

Y-DECODER

X-DECODER

I/O BUFFERS

AND LATCHES

CONTROL AND

PROTECTION LOGIC

SRAM

DATA BUFFER

INTERFACE

CONTROL

AND

LOGIC

HOLD

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