ES1010SI datasheet(6/11 Pages) ALTERA

6 / 11 page

Page 6

ES1010SI 12V Hot-Swap Power Distribution Controllers

March 2014 Altera Corporation

During the soft-start and the time-out delay duration with the IC in its current limit mode, the VGS of the external N-Channel

MOSFET is reduced driving the MOSFET switch into a (linear region) high rDS(ON) state. Strike a balance between the CR limit and

the timing requirements to avoid periods when the external N-Channel MOSFETs may be damaged or destroyed due to excessive

internal power dissipation. Refer to the MOSFET SOA information in the manufacturer’s data sheet.

When driving particularly large capacitive loads a longer soft-start time to prevent current regulation upon charging and a short CR

time may offer the best application solution relative to reliability and FET MTF.

Physical layout of RSENSE resistor is critical to avoid the possibility of false overcurrent occurrences. Ideally, trace routing

between the RSENSE resistors and the IC is as direct and as short as possible with zero current in the sense lines (see Figure 1).

CORRECT

TO ISEN+ AND

CURRENT

SENSE RESISTOR

INCORRECT

FIGURE 1. SENSE RESISTOR PCB LAYOUT

RISET

09617

March 14, 2014

Rev A

ES1010SI Datasheet(PDF) 6 Page - Altera Corporation