Product Specification

SP43404

Page 3 of 10

Z=75 Ohm

Z=75 Ohm

or GND

SMA

SMA

SUPPLY

N/C

N/C

C9

0.1µF

C10

100pF

1

2

RFIN

3

DATA

4

CLK

5

LE

11

GND

12

VNEG

13

PS

14

RFOUT

15

C8

U4

MLPQ4X4

C12

0.1µF

C14

100pF

R23

10K

1

J18

1

J19

R24 0 OHM

R25

0 OHM

1

2

3

4

J20

DATA

PS

CLK

C8

LE

-VDD

VDD

VDD

Evaluation Kit

The Digital Attenuator Evaluation Kit was designed to

ease customer evaluation of the SP43404 DSA.

J9 is used in conjunction with the supplied DC cable to

negative voltage generator is desired, then connect –

is desired, then apply -3V.

J1 should be connected to the LPT1 port of a PC with

the supplied control cable. The evaluation software is

written to operate the DSA in serial mode, so switch 7

(P/S) on the DIP switch SW1 should be ON with all

other switches off. Using the software, enable or

disable

each

attenuation

setting

to

the

desired

combined attenuation.

The software automatically

programs the DSA each time an attenuation state is

enabled or disabled.

Note: Jumper J6 supplies power to the evaluation

board support circuits.

To evaluate the Power Up options, first disconnect the

control cable from the evaluation board. The control

cable must be removed to prevent the PC port from

biasing the control pins.

During power up with P/S=1 high and LE=1, the default

power-up signal attenuation is set to the value present

on the four control bits on the four parallel data inputs

(C1 to C8). This allows any one of the 32 attenuation

settings to be specified as the power-up state.

During power up with P/S=0 high and LE=0, the control

bits are automatically set to one of two possible values

presented through the PUP interface.

These two

values are selected by the power-up control bit, PUP2,

as shown in Table 6.

Pins 1 and 7 are open and may be connected to any

bias.

Figure 4. Evaluation Board Layout

Figure 5. Evaluation Board Schematic

Note: Resistor on pin 3 is required and

should be placed as close to the part

as possible to avoid package

resonance and meet error

specifications over frequency.

Figure 4. Evaluation Board Layout

Tel: +86-23-62808818

Fax: +86-23-62805284

www.si

w.com

i at.com

patsa

/ sawmkt@s p