IR3638STRPBF datasheet(13/15 Pages) IRF

13 / 15 page

IR3638SPbF

3/19/07

For this design we have:

in=5V

o=1.2V

osc=1.25V

p=1.0V

m=450umoh

o=1.0uH

o=1x470uF, ESR=10mOhm

s=400kHz

These result to:

LC=7.3kHz

ESR=33.8kHz

s/2=200kHz

Select crossover frequency:

Fo=40kHz

Since:

LC<FESR<Fo<Fs/2, typeII compensation is

selected to place the poles and zeros.

Using equations 12, 13 and 15 will result to the

following compensation values:

Select

(13)

ESR

osc

)

(

Select

(12)

Select

(15)

POLE

≤

≅

Layout Consideration

The layout is very important when designing high

frequency switching converters. Layout will affect

noise pickup and can cause a good design to

perform with less than expected results.

Start to place the power components, make all

the connection in the top layer with wide, copper

filled areas.

The inductor, output capacitor and the MOSFET

should be close to each other as possible. This

helps to reduce the EMI radiated by the power

traces due to the high switching currents through

them. Place input capacitor directly to the drain of

the high-side MOSFET, to reduce the ESR

replace the single input capacitor with two

parallel units.

The feedback part of the system should be kept

away from the inductor and other noise sources.

The

critical

bypass

components

such

capacitors for Vcc and Vc should be close to

respective pins. It is important to place the

feedback components include feedback resistors

and compensation components close to Fb and

Comp pins.

In multilayer PCB use one layer as power ground

plane and have a control circuit ground (analog

ground), to which all signals are referenced. The

goal is to localize the high current path to a

separate loop that does not interfere with the

more sensitive analog control function. These two

grounds must be connected together on the PC

board layout at a single point.

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