PI6C48543

3.3V Low Skew 1-to-4, 800MHz,

Differential to LVDS Fanout Buffer

3

PS8771B

10/02/08

Figure 1. CLK_EN Timing Diagram

Inputs

Outputs

Input to Output Mode

Polarity

CLK or PCLK

0

1

LOW

HIGH

Differential to Differential

None Inverting

1

0

HIGH

LOW

Differential to Differential

None Inverting

0

LOW

HIGH

Single Ended to Differential

None Inverting

1

HIGH

LOW

Single Ended to Differential

None Inverting

Vcc/2

0

HIGH

LOW

Single Ended to Differential

Inverting

1

LOW

HIGH

Single Ended to Differential

Inverting

Absolute Maximum Ratings

Symbol

Parameter

Conditions

Min.

Typ.

Max.

Units

Supply voltage

Referenced to GND

4.6

V

Input voltage

Referenced to GND

-0.5

Output voltage

Referenced to GND

-0.5

Storage temperature

-65

150

Notes:

1.

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress speci

fications only and correct functional operation of the device at these or any other conditions above those listed in the operational sections of

the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.

nCLK, nPCLK

CLK, PCLK

CLK_EN

nQ0:nQ3

Q0:Q3

Disabled

Enabled

08-0247