SL28EB742 datasheet(13/40 Pages) ETC2

13 / 40 page

SL28EB742

Preliminary Rev. 0.1

2.6. PCI/SRC_STP Assertion

The PCI/SRC_STP signal is an active low input used for synchronously stopping and starting the PCI outputs while

the rest of the clock generator continues to function. The set-up time for capturing PCI/SRC_STP going low is

10 ns (tSU) (refer to Figure 6). The PCIF and SRC clocks are affected by the PCI/SRC pin if their corresponding

control bit in the I2C register is set to allow them to be free running. For SRC clocks assertion description, refer to

the CPU_STP descriptions in Section 2.4 and Section 2.5.

Figure 6. PCI/SRC_STP Assertion Waveform

2.7. PCI/SRC_STP Deassertion

The deassertion of the PCI/SRC_STP signal causes all PCI and stoppable PCIF to resume running in a

synchronous manner within two PCI clock periods and after PCI/SRC_STP transitions to a high level. Similarly,

PCI/SRC_STP deassertion will cause stoppable SRC clocks to resume running. For an SRC clocks deassertion

description, refer to the CPU_STP description Section 2.4 and Section 2.5.

Figure 7. PCI/SRC_STP Deassertion Waveform

SL28EB742 Datasheet(PDF) 13 Page - List of Unclassifed Manufacturers