SCL

S

P

P

STO

condition

SDA

SCL

SDA

data

change

allowed

data

valid

data

change

allowed

data

valid

data

change

allowed

LM3555

SNVS594E – JANUARY 2009 – REVISED NOVEMBER 2011

www.ti.com

Figure 1. Data Validity Diagram

SDA. Using a larger pullup resistor results in lower switching current with slower edges, while using a smaller

pullup results in higher switching currents with faster edges.

START AND STOP CONDITIONS

defined as SDA signal transitioning from HIGH to LOW while SCL line is HIGH. A STOP condition is defined as

START conditions are equivalent, function-wise. The data on SDA line must be stable during the HIGH period of

the clock signal (SCL). In other words, the state of the data line can only be changed when CLK is LOW.

Figure 2. Start and Stop Conditions

TRANSFERRING DATA

Every byte put on the SDA line must be eight bits long, with the most significant bit (MSB) being transferred first.

Each byte of data has to be followed by an acknowledge bit. The acknowledge related clock pulse is generated

by the master. The master releases the SDA line (HIGH) during the acknowledge clock pulse. The LM3555 pulls

down the SDA line during the 9th clock pulse, signifying an acknowledge. The LM3555 generates an

acknowledge after each byte has been received.

eighth bit which is a data direction bit (R/W). The LM3555 address is 30h. For the eighth bit, a “0” indicates a

WRITE and a “1” indicates a READ. The second byte selects the register to which the data will be written. The

third byte contains data to write to the selected register.

18

Submit Documentation Feedback

Copyright © 2009–2011, Texas Instruments Incorporated

Product Folder Links: LM3555