PAC5220 datasheet(39/73 Pages) ACTIVE-SEMI

39 / 73 page

PAC5220

Power Application Controller

delay.

For bootstrapped high-side operation, connect an appropriate capacitor between DRBx and DRSx and a

properly rated bootstrap diode from VP to DRBx. To operate the DRHx output as a low-side gate driver, connect

its DRBx pin to VP and its DRSx pin to VSSP.

12.3.3. High-Side Switching Transients

Typical high-side switching transients are shown in Figure 12-3(a). To ensure functionality and reliability, the

DRSx and DRBx pins must not exceed the peak and undershoot limit values shown. This should be verified by

probing the DRBx and DRSx pins directly relative to VSS pin. A small resistor and diode clamp for the DRSx pin

can be used to make sure that the pin voltage stays within the negative limit value. In addition, the high-side

slew rate dV/dt must be kept within ±5V/ns for DRSx. This can be achieved by adding a resistor-diode pair in

series, and an optional capacitor in parallel with the power switch gate. The parallel capacitor also provides a

low impedance and close gate shunt against coupling from the switch drain. These optional protection and slew

rate control are shown in Figure 12-3(b).

12.3.4. Open-Drain Drivers

The OHIx pin can be configured to be a 40V/40mA or 40V/15mA open-drain driver output, or a logic input. When

configured as an open-drain driver output, the OHIx pin can be controlled by either a register bit or a

configurable digital signal matrix (CDSM) signal. With default polarity, the OHIx pin is switched to VSSP with

17.5Ω (40mA mode) or 50Ω (15mA mode) impedance in the on state when the corresponding bit or signal is '1',

and is in the high-impedance off state when the corresponding bit or signal is '0'. When configured as an input,

the OHIx pin signal can flow to a register bit or to a CDSM signal. The polarity bit determines the signal polarity

in both input and output modes.

12.3.5. Power Drivers Control

All power drivers are initially disabled from power-on-reset. To enable the power drivers, the microprocessor

must first set the driver enable bit to '1'. The gate drivers are controlled by the microcontroller ports and/or PWM

signals according to Table 12-2, with configurable delays as shown in Table 12-3. The OHIx open-drain drivers

are controlled by their corresponding register bits. Refer to the PAC application notes and user guide for

additional information on power drivers control programming.

- 39 -

Rev 1.0‒February 25, 2014

Figure 12-3. High-Side Switching Transients and Optional Circuitry

DRSx

≥ -5V

DRBx

≤ 65V

DRBx

dV/dt

(a) High-Side Switching Transients

(b) Optional Transient Protection and Slew Rate Control

DRHx

DRLx

DRSx

DRBx

PAC5220

PAC5220 Datasheet(PDF) 39 Page - Active-Semi, Inc

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