Application information

ST1S32

20/29

Doc ID 023246 Rev 1

Figure 8.

Switching losses

5.5

Layout considerations

The PC board layout of the switching DC/DC regulator is very important to minimize the

noise injected in high impedance nodes, to reduce interference generated by the high

switching current loops and to optimize the reliability of the device.

In order to avoid EMC problems, the high switching current loops must be as short as

possible. In the buck converter there are two high switching current loops: during the ON-

time, the pulsed current flows through the input capacitor, the high-side power switch, the

inductor and the output capacitor; during the OFF-time, through the low-side power switch,

the inductor and the output capacitor.

The input capacitor connected to VINSW must be placed as close as possible to the device,

to avoid spikes on VINSW due to the stray inductance and the pulsed input current.

In order to prevent dynamic unbalance between VINSW and VINA, the trace connecting the

VINA pin to the input must be derived from VINSW.

The feedback pin (FB) connection to the external resistor divider is a high impedance node,

so interference can be minimized by routing the feedback node with a very short trace and

as far as possible from the high current paths.

A single point connection from signal ground to power ground is suggested.

Thanks to the exposed pad of the device, the ground plane helps to reduce the thermal

resistance junction-to-ambient; so a large ground plane, soldered to the exposed pad,

enhances the thermal performance of the converter allowing high power conversion.

V

SW

I

SW,HS

V

IN

V

DS,HS

P

COND,HS

P

COND,LS

P

SW

T

FALL

T

RISE

AM11422v1