2

HCPL-0872 Digital Interface IC

Because the two inputs are multiplexed, only one con-

version at a time can be made and not all features are

available for the second channel. The available features

for both channels are shown in the table below

Pin Description, Digital Interface IC

Symbol

Description

CCLK

Clock input for the Serial Configuration Interface (SCI). Serial Configuration data is clocked in on the

rising edge of CCLK.

CLAT

Latch input for the Serial Configuration Interface (SCI). The last 8 data bits clocked in on CDAT by

CCLK are latched into the appropriate configuration register on the rising edge of CLAT.

CDAT

Data input for the Serial Configuration Interface (SCI). Serial configuration data is clocked in MSB

first.

MCLK1

Channel 1 Isolated Modulator clock input. Input Data on MDAT1 is clocked in on the rising edge of

MCLK1.

MDAT1

Channel 1 Isolated Modulator data input.

MCLK2

Channel 2 Isolated Modulator clock input. Input Data on MDAT2 is clocked in on the rising edge of

MCLK2.

MDAT2

Channel 2 Isolated Modulator data input.

GND

Digital ground.

VDD

Supply voltage (4.5 V to 5.5 V).

CHAN

Channel select input. The input level on CHAN determines which channel of data is used during the

next conversion cycle. An input low selects channel 1, a high selects channel 2.

SCLK

Serial clock input. Serial data is clocked out of SDAT on the falling edge of SCLK.

SDAT

Serial data output. SDAT changes from high impedance to a logic low output at the start of a conver-

sion cycle. SDAT then goes high to indicate that data is ready to be clocked out. SDAT returns to a

high-impedance state after all data has been clocked out and CS has been brought high. SDAT goes

high immediately after RESET is released.

CS

Conversion start input. Conversion begins on the falling edge of CS. CS should remain low during

the entire conversion cycle and then be brought high to conclude the cycle.

THR1

Continuous, programmable-threshold detection for channel 1 input data. A high level output on

THR1 indicates that the magnitude of the channel 1 input signal is beyond a user programmable

threshold level between 160 mV and 310 mV. This signal continuously monitors channel 1 indepen-

dent of the channel select (CHAN) signal.

OVR1

High speed continuous over-range detection for channel 1 input data. A high level output on OVR1

indicates that the magnitude of the channel 1 input is beyond full-scale. This signal continuously

monitors channel 1 independent of the CHAN signal.

RESET

Master reset input. A logic high input for at least 100 ns asynchronously resets all configuration reg-

isters to their default values and zeroes the Offset Calibration registers.

5

6

12

11

MDAT1

MCLK2

CS

THR1

CON-

VERSION

INTER-

FACE

CONFIG.

INTER-

FACE

7

10

MDAT2

OVR1

8

9

GND

RESET

1

2

16

15

CCLK

CLAT

CHAN

3

14

CDAT

SCLK

4

13

MCLK1

SDAT

CH1

CH2

THRES-

HOLD

DETECT

&

RESET

Feature

Channel 1

Channel 2

Conversion Mode

•

•

Offset Calibration

•

•

Pre-Trigger Mode

•

Over-Range Detection

•

Adjustable Threshold

Detection

•