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TDA8020HLC2 Datasheet(PDF) 21 Page - NXP Semiconductors |
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TDA8020HLC2 Datasheet(HTML) 21 Page - NXP Semiconductors |
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21 / 28 page ![]() 2003 Nov 06 21 Philips Semiconductors Product specification Dual IC card interface TDA8020HL Notes 1. Two ceramic multilayer capacitors of minimum 100 nF with low ESR should be used in order to meet these specifications. 2. Pin I/O1 has an internal 14 k Ω pull-up resistor to VCC1 and pin I/O2 has an internal 14 kΩ pull-up resistor to VCC2. 3. Pins I/O1uC and I/O2uC have an internal 11 k Ω pull-up resistor to VDDI. 4. The hold time required (not greater than 300 ns) to bridge the undefined region of the falling edge of SCL must be internally provided by a transmitter. tHD;DAT data hold time note 4 0 −− ns tSU;DAT data set-up time 100 −− ns tr rise time SDA and SCL −− 300 ns tf fall time SDA and SCL −− 300 ns tSU;STO set-up time STOP condition 0.6 −− µs SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT handbook, full pagewidth MBC622 SDA SCL P STOP condition SDA SCL S START condition Fig.6 START and STOP conditions. handbook, full pagewidth SDA MGA728 SDA SCL t SU;STA t SU;STO t HD;STA t BUF t LOW t HD;DAT t HIGH t r t f t SU;DAT Fig.7 I2C-bus timing waveforms. |
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