* In reading data byte from HT1380/HT1381 register, the first data bit to be transmitted at the first

falling edge after the last bit of the command byte is written.

HT1380/HT1381

8

October 2, 1999

ST AR T

EN D

In p u t th e w ri t e

prot ec t c o m m and

by t e 8 E H

D i s abl e t h e w ri t e

prot ec t bi t ( W P )

by s et t i ng t h e M S B

of regi s t e r 7 t o z e r o

I npu t t he w ri t e

c o m m and b y t e 8 0 H

E nabl e t h e os c i l l a t or

by s et t i ng t h e M S B of

r egi s t er 0 t o z e ro

ST AR T

D i s abl e t h e w ri t e prot ec t

bi t a nd enab l e t he o s c i l l a t o r

R ead o r w r i t e t h e

c o rr es po ndi ng regi s t er dat a

b y te s ta rti n g w i th b i t 0

*

I npu t t h e c o m m and

b y te s ta rti n g w i th b i t 0

ST AR T

R ead o r w ri t e al l regi s t er

dat a by t e ( 64 d a t a b i t s ) i n

t he H T 1381 s t art i ng w i t h

bi t 0 of regi s t er 0

*

I npu t t h e burs t m o d e

c o m m and b y t e ( $ B E o r

$ B F ) s ta rti n g w i th b i t 0

EN D

D i s abl e t h e w ri t e prot ec t

bi t a nd enab l e t he o s c i l l a t o r

I f anot he r r egi s t er

i s a cce sse d

EN D

Ye s

No

Se t R E S T p i n

f rom l o w t o hi gh

Re s e t R E S T p i n

f rom h i gh t o l o w

Se t R E S T p i n

f rom l o w t o hi gh

Re s e t R E S T p i n

f rom h i gh t o l o w

R e s e t R E S T p i n

fro m h i g h to l o w

Se t R E S T p i n

f rom l o w t o hi gh

Se t R E S T p i n

f rom l o w t o hi gh

R e s e t R E S T p i n

f rom h i gh t o l o w

·

To disable the write

protect (WP=0) bit and

enable the oscillator

(CH=0)

·

Single byte data

transfer

·

Burst mode data

transfer