AT91SAM_14 datasheet(29/50 Pages) ATMEL

29 / 50 page

SAM7S Series [DATASHEET]

6175KS–ATARM–25-Oct-12

9.2

Clock Generator

The Clock Generator embeds one low-power RC Oscillator, one Main Oscillator and one PLL with the following

characteristics:

RC Oscillator ranges between 22 kHz and 42 kHz

Main Oscillator frequency ranges between 3 and 20 MHz

Main Oscillator can be bypassed

PLL output ranges between 80 and 220 MHz

It provides SLCK, MAINCK and PLLCK.

Figure 9-3. Clock Generator Block Diagram

9.3

Power Management Controller

The Power Management Controller uses the Clock Generator outputs to provide:

the Processor Clock PCK

the Master Clock MCK

the USB Clock UDPCK (not present on SAM7S32/16)

all the peripheral clocks, independently controllable

three programmable clock outputs

The Master Clock (MCK) is programmable from a few hundred Hz to the maximum operating frequency of the device.

The Processor Clock (PCK) switches off when entering processor idle mode, thus allowing reduced power consumption

while waiting for an interrupt.

Embedded

Oscillator

Main

Oscillator

PLL and

Divider

Clock Generator

Power

Management

Controller

XIN

XOUT

PLLRC

Slow Clock

SLCK

Main Clock

MAINCK

PLL Clock

PLLCK

Control

Status

AT91SAM Datasheet(PDF) 29 Page - ATMEL Corporation

AT91SAM Datasheet(HTML) 29 Page - ATMEL Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

Datasheet Download

Link URL