ATMEGA64A datasheet(21/395 Pages) ATMEL

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ATmega64A [DATASHEET]

8160D–AVR–02/2013

• A15:8: High-order address bus (configurable number of bits).

• ALE: Address latch enable.

•RD: Read strobe.

•WR: Write strobe.

The control bits for the External Memory Interface are located in three registers, the MCU Control Register –

MCUCR, the External Memory Control Register A – XMCRA, and the External Memory Control Register B –

XMCRB.

When the XMEM interface is enabled, the XMEM interface will override the setting in the Data Direction Registers

that corresponds to the ports dedicated to the XMEM interface. For details about the port override, see the alter-

nate functions in section “I/O Ports” on page 65. The XMEM interface will auto-detect whether an access is internal

or external. If the access is external, the XMEM interface will output address, data, and the control signals on the

ports according to Figure 8-6 (this figure shows the wave forms without wait states). When ALE goes from high-to-

low, there is a valid address on AD7:0. ALE is low during a data transfer. When the XMEM interface is enabled,

also an internal access will cause activity on address-, data- and ALE ports, but the RD and WR strobes will not

toggle during internal access. When the external memory interface is disabled, the normal pin and data direction

settings are used. Note that when the XMEM interface is disabled, the address space above the internal SRAM

boundary is not mapped into the internal SRAM. Figure 8-5 illustrates how to connect an external SRAM to the

AVR using an octal latch (typically 74 x 573 or equivalent) which is transparent when G is high.

8.5.4

Address Latch Requirements

Due to the high-speed operation of the XRAM interface, the address latch must be selected with care for system

frequencies above 8 MHz @ 4V and 4 MHz @ 2.7V. When operating at conditions above these frequencies, the

typical old style 74HC series latch becomes inadequate. The external memory interface is designed in compliance

to the 74AHC series latch. However, most latches can be used as long they comply with the main timing parame-

ters. The main parameters for the address latch are:

• D to Q propagation delay (t

pd).

• Data setup time before G low (t

su).

• Data (address) hold time after G low (

th).

The external memory interface is designed to guaranty minimum address hold time after G is asserted low of t

h = 5

ns (refer to t

LAXX_LD/tLLAXX_ST in Table 29-8 to Table 29-15 on page 315). The D to Q propagation delay (tpd) must be

taken into consideration when calculating the access time requirement of the external component. The data setup

time before G low (t

su) must not exceed address valid to ALE low (tAVLLC) minus PCB wiring delay (dependent on

the capacitive load).

Figure 8-5.

External SRAM Connected to the AVR

D[7:0]

A[7:0]

A[15:8]

SRAM

AD7:0

ALE

A15:8

AVR

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