GMS30C2116 datasheet(21/322 Pages) HYNIX

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ARCHITECTURE

1-1

1. Architecture

1.1 Introduction

1.1.1 RISC Architecture

In the early days of computer history, most computer families started with an instruction

set which was rather simple. The main reason for being simple then was the high cost for

hardware. The hardware cost has dropped and the software cost has gone up steadily in the

past three decades.

The net result is that more and more functions have been built into the hardware, making

the instruction set very large and very complex. The growth of instruction sets was also

encouraged by the popularity of microprogrammed control in the 1960s and 1970s. Even

user-defined instruction sets were implemented using microcodes in some processors for

special-purpose applications.

The evolution of computer architectures has been dominated by families of increasingly

complex processors. Under market pressures to preserve existing software, Complex

Instruction Set Computer (CISC) architectures evolved by the gradual addition of

microcode and increasingly elaborate operations. The intent was to supply more support

for high-level languages and operating systems, as semiconductor advances made it

possible to fabricate more complex integrated circuits. It seemed self-evident that

architectures should become more complex as these technological advances made it

possible to hold more complexity on VLSI devices.

In recent years, however, Reduced Instruction Set Computer (RISC) architectures have

implemented a much more sophisticated handling of the complex interaction between

hardware, firmware and software. RISC concepts emerged from statistical analysis of how

software actually uses the resources of a processor. Dynamic measurement of system

kernels and object modules generated by optimizing compilers show an overwhelming

predominance of the simplest instruction, even in the code for CISC machine. Complex

instructions are often ignored because a single way of performing a complex operation

needs of high-level language and system environments. RISC designs eliminate the

microcoded routines and turn the low-level control of the machine over to software.

This approach is not new. But its application is more universal in recent years thanks to the

prevalence of high-level languages, the development of compilers that can optimize at the

microcode level, and dramatic advances in semiconductor memory and packaging. It is

now feasible to replace machine microcode ROM with faster RAM, organized as an

instruction cache. Machine control then resides in the instruction cache and is, in fact,

customized on the fly. The instruction stream generated by system- and compiler-generated

code provides a precise fit between the requirements of high-level software and the

capabilities of the hardware. So compilers are playing a vital role in RISC performance.

The advantage of RISC architecture is described as follows:

l Simplicity made VLSI implementation possible and thus higher clock rates.

l Hardwired control and separated data and program caches lower the average CPI

(Cycles per Instruction) significantly.

l Dynamic instruction count in a RISC program only increased slightly (less than 2) in

ordinary program.

GMS30C2116 Datasheet(PDF) 21 Page - Hynix Semiconductor

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