AT80SND2CMP3B datasheet(152/242 Pages) ATMEL

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152

4341H–MP3–10/07

AT8xC51SND2C/MP3B

Table 18-11. MMSTA Register

MMSTA (S:DEh Read Only) – MMC Control and Status Register

Reset Value = 0000 0000b

CBUSY

CRC16S

DATFS

CRC7S

RESPFS

CFLCK

Bit Number

Bit

Mnemonic

Description

7 - 6

Reserved

The value read from these bits is always 0. Do not set these bits.

CBUSY

Card Busy Flag

Set by hardware when the card sends a busy state on the data line.

Cleared by hardware when the card no more sends a busy state on the data line.

CRC16S

CRC16 Status Bit

Transmission mode

Set by hardware when the token response reports a good CRC.

Cleared by hardware when the token response reports a bad CRC.

Reception mode

Set by hardware when the CRC16 received in the data block is correct.

Cleared by hardware when the CRC16 received in the data block is not correct.

DATFS

Data Format Status Bit

Transmission mode

Set by hardware when the format of the token response is correct.

Cleared by hardware when the format of the token response is not correct.

Reception mode

Set by hardware when the format of the frame is correct.

Cleared by hardware when the format of the frame is not correct.

CRC7S

CRC7 Status Bit

Set by hardware when the CRC7 computed in the response is correct.

Cleared by hardware when the CRC7 computed in the response is not correct.

This bit is not relevant when CRCDIS is set.

RESPFS

Response Format Status Bit

Set by hardware when the format of a response is correct.

Cleared by hardware when the format of a response is not correct.

CFLCK

Command FIFO Lock Bit

Set by hardware to signal user not to write in the transmit command FIFO: busy state.

Cleared by hardware to signal user the transmit command FIFO is available: idle state.

AT80SND2CMP3B Datasheet(PDF) 152 Page - ATMEL Corporation

AT80SND2CMP3B Datasheet(HTML) 152 Page - ATMEL Corporation

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