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AT80SND2CMP3B Datasheet(PDF) 154 Page - ATMEL Corporation

Part # AT80SND2CMP3B
Description  MPEG I/II-Layer 3 Hardwired Decoder
PDF  242 Pages
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Manufacturer  ATMEL [ATMEL Corporation]
Direct Link  http://www.atmel.com
Logo ATMEL - ATMEL Corporation

AT80SND2CMP3B Datasheet(HTML) 154 Page - ATMEL Corporation

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154
4341H–MP3–10/07
AT8xC51SND2C/MP3B
Table 18-13. MMMSK Register
MMMSK (S:DFh) – MMC Interrupt Mask Register
Reset Value = 1111 1111b
Table 18-14. MMCMD Register
MMCMD (S:DDh) – MMC Command Register
Reset Value = 1111 1111b
7
6
5
4
3
2
1
0
MCBM
EORM
EOCM
EOFM
F2FM
F1FM
F2EM
F1EM
Bit Number
Bit
Mnemonic
Description
7
MCBM
MMC Card Busy Interrupt Mask Bit
Set to prevent MCBI flag from generating an MMC interrupt.
Clear to allow MCBI flag to generate an MMC interrupt.
6
EORM
End Of Response Interrupt Mask Bit
Set to prevent EORI flag from generating an MMC interrupt.
Clear to allow EORI flag to generate an MMC interrupt.
5
EOCM
End Of Command Interrupt Mask Bit
Set to prevent EOCI flag from generating an MMC interrupt.
Clear to allow EOCI flag to generate an MMC interrupt.
4
EOFM
End Of Frame Interrupt Mask Bit
Set to prevent EOFI flag from generating an MMC interrupt.
Clear to allow EOFI flag to generate an MMC interrupt.
3
F2FM
FIFO 2 Full Interrupt Mask Bit
Set to prevent F2FI flag from generating an MMC interrupt.
Clear to allow F2FI flag to generate an MMC interrupt.
2
F1FM
FIFO 1 Full Interrupt Mask Bit
Set to prevent F1FI flag from generating an MMC interrupt.
Clear to allow F1FI flag to generate an MMC interrupt.
1
F2EM
FIFO 2 Empty Interrupt Mask Bit
Set to prevent F2EI flag from generating an MMC interrupt.
Clear to allow F2EI flag to generate an MMC interrupt.
0
F1EM
FIFO 1 Empty Interrupt Mask Bit
Set to prevent F1EI flag from generating an MMC interrupt.
Clear to allow F1EI flag to generate an MMC interrupt.
7
6
5
4
3
2
1
0
MC7
MC6
MC5
MC4
MC3
MC2
MC1
MC0
Bit Number
Bit
Mnemonic
Description
7 - 0
MC7:0
MMC Command Receive Byte
Output (read) register of the response FIFO.
MMC Command Transmit Byte
Input (write) register of the command FIFO.



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