HMS39C7092 datasheet(89/199 Pages) HYNIX

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Flash MCU(HMS39C7092)

Interrupt controller

Preliminary

FSR

FIQ Status Register (0x0900_1210 Read Only)

b31 -

b25 b24b23b22b21b20b19b18b17b16b15b14b13b12b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0

FSR

Reserved

I24 I23 I22 I21 I20 I19 I18 I17 I16 I15 I14 I13 I12 I11 I10 I9

Reset

0000000

Initial value : 0x00000000

Bit field I0-I24

1 : FIQ Pending

0 : FIQ Idle

The FIQ status register is used to reflect the status of all channels set to produce an

FIQ interrupt (IDRn = 1). When an interrupt is set for an FIQ occurring, the

corresponding bit is set in FIQ status register. The interrupt handler will examine this

clear register is written to ‘1’, the corresponding bit is cleared if that channel is

configured to edge trigger mode. A HIGH bit indicates that the interrupt is active and

will generate an interrupt to the processor.

ISR

IRQ Status Register (0x0900_1214 Read Only)

b31 -

b25 b24b23b22b21b20b19b18b17b16b15b14b13b12b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0

ISR

Reserved

I24 I23 I22 I21 I20 I19 I18 I17 I16 I15 I14 I13 I12 I11 I10 I9

Reset

0000000

Initial value : 0x00000000

Bit field I0-I24

1 : IRQ Pending

0 : IRQ Idle

The IRQ status register is used to reflect the status of all channels set to produce an

IRQ interrupt (IDR(i) = 0). When an interrupt is set for an IRQ occurring, the

corresponding bit is set in IRQ status register. The interrupt handler will examine this

clear register is written to ‘1’, the corresponding bit is cleared if that channel is

configured to edge trigger mode. A HIGH bit indicates that the interrupt is active and

will generate an inte rrupt to the processor.

FMR

FIQ Mask Register (0x0900_1218 R/W)

b31 -

b25 b24b23b22b21b20b19b18b17b16b15b14b13b12b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0

FMR

Reserved

I24 I23 I22 I21 I20 I19 I18 I17 I16 I15 I14 I13 I12 I11 I10 I9

Reset

0000000

Initial value : 0x00000000

Bit field I0-I24

1 : Disable FIQ

0 : Enable FIQ

The FIQ request mask register is used to mask the request to generate an interrupt

to a processor. If certain bits within the interrupt controller are not implemented, the

corresponding bits in the FIQ reques t mask register must be masked. A bit value 0

indicates that the interrupt is unmasked and will allow an interrupt request to reach

the processor. A bit value 1 indicates that the interrupt is masked. On reset, all FIQ

requests are unmasked.

HMS39C7092 Datasheet(PDF) 89 Page - Hynix Semiconductor

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