AD1815

–21–

REV. 0

FMVO

FM Synthesis Valid Out. This bit is set if Slots 6 and 7 contain valid left and right FM synthesis data.

SSPVO

SS/SB Playback Valid Out. This bit is set if Slots 4 and 5 contain valid right and left SS/SB playback data.

SSCVO

SS/SB Capture Valid Out. This bit is set if valid SS/SB capture data is being transmitted. If not in a modem mode,

Slots 2 and 3 will contain valid right and left SS/SB capture data. If in modem mode, only Slot 3 will contain valid

left SS/SB capture data as Slot 2 and the ADC right channel are used by the modem.

MODVO

Modem Valid Out. This bit is set if Slot 2 contains valid modem capture data.

PNPR

Plug and Play Reset flag. This bit is set by an AD1815 reset (RESETB pin asserted LOW), or by a Plug and Play

reset command. This bit is cleared by the assertion of the FCLR bit in the control word. While this bit is set, all at-

tempts to write a SS indirect register via the DSP port will be ignored and fail. This is to insure that Plug and Play

resets are immediately applied to the application running on the DSP, without requiring them to continuously poll the

Plug and Play reset status bit. During the frame that this bit is cleared (by asserting FCLR), an attempt to write a

SS indirect register will succeed. If the FCLR bit is asserted continuously, writes to indirect registers via the DSP

port will always be enabled. A Plug and Play reset command will set this PNPR bit HIGH during at least one

frame.

PDN

Powerdown flag. This bit is set by an AD1815 reset (RESETB pin asserted LOW), or by an AD1815 powerdown.

Before an AD1815 powerdown sequence shuts down the DSP port, at least one frame will be sent with this bit set.

This bit can be cleared by the assertion of the FCLR (DSP port status clear) bit in the control word, providing the

AD1815 is no longer in powerdown.

The SDFS pin is used for the serial interface frame synchronization. New frames are marked by a one SCLK duration HI pulse

driven out on SDFS one serial clock period before the frame begins. Upon initializing, there are exactly 12 time slots per frame, and

16 bits per time slot. The frame rate is 57,291 and 2/3 Hz (11 MHz SCLK / (16 bits * 12 slots). The frame rate can also be changed

from the default value by reprogramming the rate in registers. The frame rate can run at the default rate or programmed to match the

modem sample rate, ADC capture rate, DAC playback rate, music sample rate, I

frame rate is not equivalent to the sample rate, Valid Out, Request In, and Valid In bits are used to control the sample data flow.

When the frame rate is equivalent to the sample rate, Valid and Request bits can be ignored.

SCLK

SDI OR SDO

15 14 13

3

2

1

0 15 14 13

3

2

1

0 15 14 13

3

2

1

0

SDFS

SLOT 0

SLOT 15

SLOT 0

SLOT 15

SLOT 0

SLOT 15

SAMPLE PERIOD N + 2

SAMPLE PERIOD N + 1

SAMPLE PERIOD N

Figure 12. DSP Serial Interface (Default Frame Rate)

SCLK

15 14 13

3 2

1

0

15 14 13

3 2

1

0

15 14 13

3 2

1

0

SLOT 0

SLOT 15

SLOT 0

SLOT 15

SLOT 0

SLOT 15

SAMPLE PERIOD N + 2

SAMPLE PERIOD N + 1

SAMPLE PERIOD N

SDI OR SDO

SDFS

Figure 13. DSP Serial Interface (User Programmed Frame Rate)