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IDT74FCT810CTEB Datasheet(PDF) 4 Page - Integrated Device Technology

Part # IDT74FCT810CTEB
Description  FAST CMOS BUFFER/CLOCK DRIVER
PDF  6 Pages
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Manufacturer  IDT [Integrated Device Technology]
Direct Link  http://www.idt.com
Logo IDT - Integrated Device Technology

IDT74FCT810CTEB Datasheet(HTML) 4 Page - Integrated Device Technology

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IDT54/74FCT810BT/CT
FAST CMOS BUFFER/CLOCK DRIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
9.4
4
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
(3,4)
NOTES:
1. See test circuits and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. tPLH, tPHL, tSK(t) are production tested. All other parameters guaranteed but not production tested.
4. Propagation delay range indicated by Min. and Max. limit is due to VCC, operating temperature and process parameters. These propagation delay
limits do not imply skew.
3103 tbl 06
IDT54/74FCT810BT
IDT54/74FCT810CT
Com'l.
Mil.
Com'l.
Mil.
Symbol
Parameter
Condition(1) Min.
(2)
Max. Min.(2)
Max. Min.(2)
Max.
Min.(2) Max.
Unit
tPLH
tPHL
Propagation Delay
INA to OAn, INB to
OBn
CL = 50pF
RL = 500
Ω
1.5
4.5
1.5
4.9
1.5
4.3
1.5
4.6
ns
tR
Output Rise Time
—
1.5
—
2.0
—
1.5
—
2.0
ns
tF
Output Fall Time
—
1.5
—
1.5
—
1.5
—
1.5
ns
tSK1(o) Output skew (same bank): skew between
outputs of same bank and same package
(same transition)
—
0.5
—
0.9
—
0.3
—
0.7
ns
tSK2(o) Output skew (all banks): skew between
outputs of all banks of same package
(inputs tied together)
—
0.7
—
1.1
—
0.6
—
1.0
ns
tSK(p)
Pulse skew: skew between opposite
transitions of same output |(tPHL-tPLH)|
—
0.7
—
1.2
—
0.7
—
1.1
ns
tSK(t)
Package skew: skew between outputs of
different packages at same power supply
voltage, temperature, package type and
speed grade
—
1.2
—
1.5
—
1.0
—
1.2
ns
tPZL
tPZH
Output Enable Time
OEA to OAn, OEB to OBn
1.5
6.0
1.5
6.5
1.5
5.0
1.5
6.0
ns
tPLZ
tPHZ
Output Disable Time
OEA to OAn, OEB to OBn
1.5
6.0
1.5
6.5
1.5
5.0
1.5
6.0
ns



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