E28F002BVT80 datasheet(29/55 Pages) INTEL

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2-MBIT SmartVoltage BOOT BLOCK FAMILY

SEE NEW DESIGN RECOMMENDATIONS

4.2.1

APPLYING VCC VOLTAGES

When applying VCC voltage to the device, a delay

may be required before initiating device operation,

depending on the VCC ramp rate. If VCC ramps

slower than 1V/100 µs (0.01 V/µs) then no delay is

required. If VCC ramps faster than 1V/100 µs (0.01

V/µs), then a delay of 2 µs is required before

initiating

device

operation.

RP#

GND

recommended during power-up to protect against

spurious write signals when VCC is between VLKO

and VCCMIN.

VCC Ramp Rate

Required Timing

≤ 1V/100 µs

No delay required.

> 1V/100

µs

A delay time of 2

µs is required before any device operation is initiated, including read

operations, command writes, program operations, and erase operations. This delay is

measured beginning from the time VCC reaches VCCMIN (3.0 V for 3.3

± 0.3 V operation;

and 4.5 V for 5 V operation).

NOTES:

These requirements must be strictly followed to guarantee all other read and write specifications.

To switch between 3.3 V and 5 V operation, the system should first transition VCC from the existing voltage range to GND,

and then to the new voltage. Any time the VCC supply drops below VCCMIN, the chip may be reset, aborting any operations

pending or in progress.

These guidelines must be followed for any VCC transition from GND.

4.3

Capacitance

TA = 25 °C, f = 1 MHz

Symbol

Parameter

Note

Typ

Max

Unit

Conditions

CIN

Input Capacitance

VIN = 0 V

COUT

Output Capacitance

1, 2

VOUT = 0 V

NOTES:

1. Sampled, not 100% tested.

2. For the 28F002B, address pin A10 follows the COUT capacitance numbers.

E28F002BVT80 Datasheet(PDF) 29 Page - Intel Corporation

E28F002BVT80 Datasheet(HTML) 29 Page - Intel Corporation

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