E28F004BVB60 datasheet(39/57 Pages) INTEL

39 / 57 page

4-MBIT SmartVoltage BOOT BLOCK FAMILY

PRELIMINARY

NOTES:

1. Read timing characteristics during write and erase operations are the same as during read-only operations. Refer to AC

characteristics during read mode.

2. The on-chip WSM completely automates program/erase operations; program/erase algorithms are now controlled internally

which includes verify and margining operations.

3. Refer to command definition table for valid A

IN. (Table 7)

4. Refer to command definition table for valid D

IN. (Table 7)

5. Program/erase durations are measured to valid SRD data (successful operation, SR.7 = 1).

6. For boot block program/erase, RP# should be held at V

HH or WP# should be held at VIH until operation completes

successfully.

7. Time t

PHBR is required for successful locking of the boot block.

8. Sampled, but not 100% tested.

9. See Test Configurations (Figure 14), 3.3V Standard Test component values.

10. See Test Configurations (Figure 14), 5V High-Speed Test component values.

11. See Test Configurations (Figure 14), 5V Standard Test component values.

ADDRESSES (A)

CE# (E)

OE# (G)

WE# (W)

DATA (D/Q)

RP# (P)

6.5V

WHEH

WHWL

Valid

SRD

WHQV1,2,3,4

PHHWH

PHWL

High Z

WHDX

(V)

PPH

PPLK

PPH

WP#

AVAV

AVWH

WHAX

DVWH

WLWH

QVPH

QVVL

VPWH

ELWL

0530_17

NOTES:

1. VCC Power-Up and Standby.

2. Write Program or Erase Setup Command.

3. Write Valid Address and Data (Program) or Erase Confirm Command.

4. Automated Program or Erase Delay.

5. Read Status Register Data.

6. Write Read Array Command.

Figure 17. AC Waveforms for Write Operations (WE#–Controlled Writes)

E28F004BVB60 Datasheet(PDF) 39 Page - Intel Corporation

E28F004BVB60 Datasheet(HTML) 39 Page - Intel Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57

Datasheet Download

Link URL