80960HA datasheet(81/102 Pages) INTEL

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80960HA/HD/HT

Advance Information Datasheet

Figure 59. Bus States

Ti = IDLE

Th = HOLD

Ta = ADDRESS

Td = DATA

Tb = BOFF’ed

Taw= address to data wait

To = ONCE

Td1

Taw2

Trw4

Tdw3

Tdw= data to data wait

Tdw= data to address wait

!BOFF and READ and Nrdd =0

READ and Nrdd >0 or

WRITE and Nwdd >0

BOFF

WdCNT = 1

!BOFF and

WaCNT = 1

WxCNT=1 and

HOLD

WxCNT > 1

BOFF

!BOFF

HOLD

!HOLD

NOTE:

1. When the PMCON for the region has External Ready Control enabled, wait states are inserted as

long as READY and BTERM are de-asserted. When Read Pipelining is enabled, the Ta state of the

subsequent read access is concurrent with the last data cycle of the access. Because External

Ready Control is disabled for Read Pipelining, the address cycle occurs during BLAST.

2. WaCNT is decremented during Taw

3. WdCNT is decremented during Tdw

4. WxCNT is decremented during Trw

!HOLD and WxCNT=1

and !REQUEST

!HOLD and WxCNT=1

and REQUEST

!RESET and

!HOLD and

REQUEST

RESET and

ONCE and

RESET

WaCNT > 1

READ and Nrad >0 or

WRITE and Nwad >0

!BOFF and READ and Nrad =0 or

!BOFF and WRITE and Nwad =0

!BOFF and READY and !BLAST or

!HOLD and BLAST and REQUEST and NXDA =0

WdCNT > 1

KEY:

!BOFF and

and Nxda=0

HOLD and BLAST

!BOFF and !HOLD and

Nxda =0

BLAST and

and !BLAST or !BOFF and

WRITE and Nwdd = 0 and !BLAST or

Nxda >0

REQUEST= One or more

requests in the bus queue.

READ= The current

access is a read.

WRITE= The current

access is a write.

RESET

BLAST and

BOFF

and !REQUEST

!ONCE

READY!

!BOFF and BTERM and !BLAST or !BOFF and

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