M80C286 datasheet(21/60 Pages) INTEL

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M80C286

Table 15 M80C286 Pointer Test Instructions

Instruction

Operands

Function

ARPL

Selector

Adjust Requested Privilege

Level adjusts the RPL of

the selector to the numeric

maximum of current selec-

tor RPL value and the RPL

value in the register Set

zero flag if selector RPL

was changed by ARPL

VERR

Selector

VERify for Read sets the

zero flag if the segment re-

ferred to by the selector

can be read

VERW

Selector

VERify for Write sets the

zero flag if the segment re-

ferred to by the selector

can be written

LSL

Load Segment Limit reads

Selector

the segment limit into the

and descriptor type allow

Set zero flag if successful

LAR

Load Access Rights reads

Selector

the

descriptor

access

rights byte into the register

if privilege rules allow Set

zero flag if successful

DOUBLE FAULT AND SHUTDOWN

If two separate exceptions are detected during a sin-

gle instruction execution the M80C286 performs the

double fault exception (8) If an execution occurs

during processing of the double fault exception the

M80C286 will enter shutdown During shutdown no

further instructions or exceptions are processed Ei-

ther NMI (CPU remains in protected mode) or RE-

SET (CPU exits protected mode) can force the

M80C286 out of shutdown Shutdown is externally

signalled via a HALT bus operation with A1 LOW

PROTECTED MODE INITIALIZATION

The M80C286 initially executes in real address

mode after RESET To allow initialization code to be

placed at the top of physical memory A23–A20 will

be HIGH when the M80C286 performs memory ref-

erences relative to the CS register until CS is

changed A23–A20 will be zero for references to the

DS ES or SS segments Changing CS in real ad-

dress mode will force A23–A20 LOW whenever CS is

used again The initial CSIP value of F000FFF0

provides 64K bytes of code space for initialization

code without changing CS

Protected mode operation requires several registers

to be initialized The GDT and IDT base registers

must refer to a valid GDT and IDT After executing

the LMSW instruction to set PE the M80C286 must

immediately execute an intra-segment JMP instruc-

tion to clear the instruction queue of instructions de-

coded in real address mode

To force the M80C286 CPU registers to match the

initial protected mode state assumed by software

execute a JMP instruction with a selector referring to

the initial TSS used in the system This will load the

task register local descriptor table register segment

registers and initial general register state The TR

should point at a valid TSS since any task switch

operation involves saving the current task state

SYSTEM INTERFACE

The M80C286 system interface appears in two

forms a local bus and a system bus The local bus

consists of address data status and control signals

at the pins of the CPU A system bus is any buffered

version of the local bus A system bus may also dif-

fer from the local bus in terms of coding of status

and control lines andor timing and loading of sig-

nals The M80C286 family includes several devices

to generate standard system buses such as the

IEEE 796 standard MULTIBUS

Bus Interface Signals and Timing

The M80C286 microsystem local bus interfaces the

M80C286 to local memory and IO components

The interface has 24 address lines 16 data lines

and 8 status and control signals

The M80C286 CPU

M82C284 clock generator

M82C288 bus controller transceivers and latches

provide a buffered and decoded system bus inter-

face The M82C284 generates the system clock and

synchronizes READY and RESET The M82C288

converts bus operation status encoded by the

M80C286 into command and bus control signals

These components can provide the timing and elec-

trical power drive levels required for most system

bus interfaces including the Multibus

Physical Memory and IO Interface

A maximum of 16 megabytes of physical memory

can be addressed in protected mode One mega-

byte can be addressed in real address mode Memo-

ry is accessible as bytes or words Words consist of

any two consecutive bytes addressed with the least

significant byte stored in the lowest address

Byte transfers occur on either half of the 16-bit local

data bus Even bytes are accessed over D7–D0

while odd bytes are transferred over D15–D8 Even-

addressed words are transferred over D15–D0 in

one bus cycle while odd-addressed word require

two bus operations The first transfers data on

D15–D8 and the second transfers data on D7–D0

Both byte data transfers occur automatically trans-

parent to software

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