8

NOTES:

†

This Timing Diagram is used to show signal relationships only, and does not represent any specific machine cycle.

†

All measurements are referenced to 50% point of the wave forms.

†

Shaded areas indicate “don’t care” or undefined state. Multiple transitions may occur during this period.

†

For the run (RAM only) mode only.

††

For the run (RAM/ROM) mode only.

FIGURE 5. TIMING WAVEFORMS

00

01

10

11

20

21

30

31

40

41

50

51

60

61

70

0

71

00

01

1

2

3

4

5

6

7

0

CLOCK

TPA

TPB

HIGH ORDER

ADDRESS BYTE

LOW ORDER

ADDRESS BYTE

MEMORY

ADDRESS

MRD

(MEMORY

READ CYCLE)

MWR

(MEMORY

WRITE CYCLE)

† ME

(MEMORY

ENABLE)

INTERNAL RAM

ACCESS TIME

†† EMS

(EXTERNAL

MEMORY

SELECT)

DATA FROM

CPU TO BUS

DATA FROM

INTERNAL MEMORY

TO BUS (ME = LOW)

STATE CODES

Q

N0, N1, N2

(I/O EXECUTION

CYCLE)

DATA LATCHED

IN CPU

DATA FROM

BUS TO CPU

DMA SAMPLED (S1, S2, S3)

DMA REQUEST

INTERRUPT

SAMPLED (S1, S2)

INTERRUPT

REQUEST

EF1 - EF4

WAIT

CLEAR

FLAG LINES

SAMPLED END OF S0

CDP1805AC, CDP1806AC