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Application Information

In a CDP1800 series microprocessor-based system where

MRD is used to distinguish between INP and OUT

instructions, an lNP instruction is assumed to occur at the

beginning of every I/O cycle because MRD starts high.

Therefore, at the start of an OUT instruction, which uses the

same 3-bit N code as that used for selection of an input port,

the input device is selected for a short time (see Figure 8).

This condition forces SR low and sets the internal SR latch

(see Figure 3). In a small system with unique N codes for

inputs and outputs, this situation does not arise. Using the

CDP1853 N-bit decoder or equivalent logic to decode the N

lines after TPA prevents dual selection in larger systems

(see Figure 9 and Figure 10).

FIGURE 8. EXECUTION OF A “65” OUTPUT INSTRUCTION SHOWING MOMENTARY SELECTION OF INPUT PORT “D”

FIGURE 9. CDP1853 TIMING WAVEFORMS

NOTE:

1. Output enabled when EN = HIGH. Internal signal shown for ref-

erence only (See Figure 1).

FIGURE10. CDP1853 FUNCTIONAL DIAGRAM

MRD

SR

SELECT

N2

N1

N0

6D

65

TPA

TPB

CE

EN

OUTPUT

(NOTE 1)

4

5

6

7

12

11

10

9

OUT 7

OUT 6

OUT 5

OUT 4

OUT 3

OUT 2

OUT 1

1 OF 8

N0

N1

N2

2

3

14

DECODER

EN

CE

13

CLOCK A

(TPA)

CLOCK B

(TPB)

1

15

Qn

OUT 0

CDP1852, CDP1852C