HIP6002 datasheet(7/12 Pages) INTERSIL

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Application Guidelines

Layout Considerations

As in any high frequency switching converter, layout is very

important. Switching current from one power device to another

can generate voltage transients across the impedances of the

interconnecting bond wires and circuit traces. These

interconnecting impedances should be minimized by using

wide, short printed circuit traces. The critical components

should be located as close together as possible, using ground

plane construction or single point grounding.

Figure 6 shows the critical power components of the converter.

To minimize the voltage overshoot, the interconnecting wires

indicated by heavy lines should be part of ground or power

plane in a printed circuit board. The components shown in

Figure 6 should be located as close together as possible.

Please note that the capacitors CIN and CO each represent

numerous physical capacitors. Locate the HIP6002 within 3

inches of the MOSFETs, Q1 and Q2. The circuit traces for the

MOSFETs’ gate and source connections from the HIP6002

must be sized to handle up to 1A peak current.

Figure 7 shows the circuit traces that require additional

layout consideration. Use single point and ground plane

construction for the circuits shown. Minimize any leakage

current paths on the SS PIN and locate the capacitor, CSS

close to the SS pin because the internal current source is

only 10

µA. Provide local VCC decoupling between VCC and

GND pins. Locate the capacitor, CBOOT as close as practical

to the BOOT and PHASE pins.

Feedback Compensation

Figure 8 highlights the voltage-mode control loop for a

synchronous-rectiﬁed buck converter. The output voltage

(VOUT) is regulated to the Reference voltage level. The error

ampliﬁer (Error Amp) output (VE/A) is compared with the

oscillator (OSC) triangular wave to provide a pulse-width

modulated (PWM) wave with an amplitude of VIN at the

PHASE node. The PWM wave is smoothed by the output

ﬁlter (LO and CO).

The modulator transfer function is the small-signal transfer

function of VOUT/VE/A. This function is dominated by a DC

Gain and the output ﬁlter (LO and CO), with a double pole

break frequency at FLC and a zero at FESR. The DC Gain of

the modulator is simply the input voltage (VIN) divided by the

peak-to-peak oscillator voltage

∆VOSC.

Modulator Break Frequency Equations

The compensation network consists of the error ampliﬁer

(internal to the HIP6002) and the impedance networks ZIN

and ZFB. The goal of the compensation network is to

provide a closed loop transfer function with the highest 0dB

crossing frequency (f0dB) and adequate phase margin.

Phase margin is the difference between the closed loop

phase at f0dB and 180 degrees. The equations below relate

the compensation network’s poles, zeros and gain to the

components (R1, R2, R3, C1, C2, and C3) in Figure 9. Use

these guidelines for locating the poles and zeros of the

compensation network:

BAND GAP

REFERENCE

1.26V

VID0

VID1

VID2

VID3

COMP

DACOUT

ERROR

AMPLIFIER

21.5k

Ω

1.7k

Ω

10.7k

Ω

5.4k

Ω

2.7k

Ω

2.9k

Ω

DAC

FIGURE 5. DAC FUNCTION SCHEMATIC

PGND

LGATE

UGATE

PHASE

VIN

VOUT

RETURN

HIP6002

CIN

FIGURE 6. PRINTED CIRCUIT BOARD POWER AND

GROUND PLANES OR ISLANDS

FIGURE 7. PRINTED CIRCUIT BOARD SMALL SIGNAL

LAYOUT GUIDELINES

+12V

HIP6002

GND

VCC

BOOT

VOUT

PHASE

+VIN

CBOOT

CVCC

CSS

•

---------------------------------------

ESR

•

()

•

---------------------------------------------

HIP6002

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