HIP6004B datasheet(8/12 Pages) INTERSIL

8 / 12 page

Figure 5 shows the critical power components of the converter.

To minimize the voltage overshoot the interconnecting wires

indicated by heavy lines should be part of ground or power

plane in a printed circuit board. The components shown in

Figure 5 should be located as close together as possible.

Please note that the capacitors CIN and CO each represent

numerous physical capacitors. Locate the HIP6004B within 3

inches of the MOSFETs, Q1 and Q2. The circuit traces for the

MOSFETs’ gate and source connections from the HIP6004B

must be sized to handle up to 1A peak current.

Figure 6 shows the circuit traces that require additional

layout consideration. Use single point and ground plane

construction for the circuits shown. Minimize any leakage

current paths on the SS PIN and locate the capacitor, CSS

close to the SS pin because the internal current source is

only 10

µA. Provide local VCC decoupling between VCC and

GND pins. Locate the capacitor, CBOOT as close as

practical to the BOOT and PHASE pins.

Feedback Compensation

Figure 7 highlights the voltage-mode control loop for a

synchronous-rectified buck converter. The output voltage

(VOUT) is regulated to the Reference voltage level. The

error amplifier (Error Amp) output (VE/A) is compared with

the oscillator (OSC) triangular wave to provide a pulse-

width modulated (PWM) wave with an amplitude of VIN at

the PHASE node.

The PWM wave is smoothed by the output filter (LO and CO).

The modulator transfer function is the small-signal transfer

function of VOUT/VE/A. This function is dominated by a DC

Gain and the output filter (LO and CO), with a double pole

break frequency at FLC and a zero at FESR . The DC Gain

of the modulator is simply the input voltage (VIN) divided by

the peak-to-peak oscillator voltage

∆VOSC.

Modulator Break Frequency Equations

The compensation network consists of the error amplifier

(internal to the HIP6004B) and the impedance networks

ZIN and ZFB. The goal of the compensation network is to

provide a closed loop transfer function with the highest 0dB

crossing frequency (f0dB) and adequate phase margin.

Phase margin is the difference between the closed loop

phase at f0dB and 180 degrees. The equations below relate

the compensation network’s poles, zeros and gain to the

components (R1, R2 , R3, C1, C2, and C3) in Figure 7. Use

these guidelines for locating the poles and zeros of the

compensation network:

1. Pick Gain (R2/R1) for desired converter bandwidth.

2. Place 1ST Zero Below Filter’s Double Pole (~75% FLC).

3. Place 2ND Zero at Filter’s Double Pole.

4. Place 1ST Pole at the ESR Zero.

5. Place 2ND Pole at Half the Switching Frequency.

6. Check Gain against Error Amplifier’s Open-Loop Gain.

7. Estimate Phase Margin - Repeat if Necessary.

PGND

LGATE

UGATE

PHASE

VIN

VOUT

RETURN

HIP6004B

CIN

FIGURE 5. PRINTED CIRCUIT BOARD POWER AND GROUND

PLANES OR ISLANDS

FIGURE 6. PRINTED CIRCUIT BOARD SMALL SIGNAL

LAYOUT GUIDELINES

+12V

HIP6004B

GND

VCC

BOOT

VOUT

PHASE

+VIN

CBOOT

CVCC

CSS

FIGURE 7. VOLTAGE-MODE BUCK CONVERTER

COMPENSATION DESIGN

VOUT

REFERENCE

ESR

VIN

∆VOSC

ERROR

AMP

PWM

DRIVER

(PARASITIC)

ZFB

DACOUT

COMP

VOUT

ZFB

HIP6004B

ZIN

COMPARATOR

DRIVER

DETAILED COMPENSATION COMPONENTS

PHASE

VE/A

ZIN

OSC

π x L

x C

-------------------------------------------

ESR

π x ESR x C

--------------------------------------------

HIP6004B

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